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rev: 102108 ds33m33 demo kit general description the ds33m33 demo kit (dk) is an easy-to-use evaluation board for the ds33m33 and the ds33m33 ethernet-over-sonet/sdh devices. the demo kit contains an option for either t3 or e3. the t3e3 links are complete with line interface, transformers, and network connections. maxims chipview software is provided with the demo kit, giving point-and-click access to configuration and status registers from a windows ? -based _ pc. on-board leds indicate receive loss-of-signal, queue overflow, ethernet link, tx/rx, and interrupt status. windows is a registered trademark of microsoft corp. demo kit contents DS33M33DK board cd including: chipview software ds33m33 definition files DS33M33DK definition file DS33M33DK data sheet ds33m33 data sheet features ? demonstrates key functions of ds33m33 ethernet transport chipset ? includes ethernet phy supporting 10/100 and gigabit modes ? includes optical sfp module for sonet/sdh interface ? network connectors, transformers, and termination ease connectivity ? careful layout provides signal integrity ? on-board processor and chipview software provide point-and-click access to the ds33m33 and ds3154 register set ? software-controlled (register mapped) configuration switches facilitate clock and signal routing ? all system side and overhead pins are easily accessible for external data source/sink ? leds programmed through gpio pins provide status ? easy-to-read silkscreen labels identify the signals associated with all connectors, jumpers, and leds ordering information part type DS33M33DK demo kit for ds33m33 ________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. downloaded from: http:///
_________________________________________________________________________________________________ DS33M33DK rev: 102108 2 of 48 table of contents 1. board floorplan ..................................................................................................................... 3 2. pc board errata....................................................................................................................... 3 3. file locations ............................................................................................................................ 4 4. basic operation ................................................................................................................ ........ 5 4.1 p owering u p the d emo k it .......................................................................................................... 5 4.1.1 general ........................................................................................................................ .......................... 5 4.2 b asic ds33m33 i nitialization ...................................................................................................... 5 4.2.1 additional configur ation for ds33m33 ........................................................................................... ........ 5 4.3 m onitor and c apture e thernet t raffic ................................................................................... 5 5. jumpers and co nnectors ..................................................................................................... 6 6. line-side connections .......................................................................................................... .. 9 7. system connectors ................................................................................................................ 9 8. microcontroller ..................................................................................................................... 9 9. power-supply connectors .................................................................................................. 9 10. connecting to a computer .................................................................................................. 9 11. installing and running the software .......................................................................... 10 12. address map .................................................................................................................... ......... 11 12.1 o verhead cpld r egister m ap .............................................................................................. 11 12.2 c ontrol and s tatus r egisters ............................................................................................ 12 13. additional information/resources................................................................................ 16 13.1 ds33m33 i nformation ............................................................................................................ 16 13.2 DS33M33DK i nformation ....................................................................................................... 16 13.3 t echnical s upport ................................................................................................................. 16 14. component list................................................................................................................. ....... 16 15. schematics ..................................................................................................................... ........... 21 list of figures figure 1-1. DS33M33DK board floorplan.......................................................................................... ......................... 3 figure 15-1. ds33m33 pcb layout and schematic hierar chy block page listing.................................................. 21 list of tables table 3-1. definition and configurati on files .................................................................................. ............................ 4 table 5-1. jumper s and conne ctors .............................................................................................. ............................. 6 table 12-1. a ddress map ........................................................................................................ .................................. 11 table 12-2. register map for overhea d cpld (reference designator u01) .......................................................... .11 downloaded from: http:///
_________________________________________________________________________________________________ DS33M33DK rev: 102108 3 of 48 1. board floorplan figure 1-1. DS33M33DK board floorplan 2. pcb errata there are no errata for the DS33M33DK02a0. microprocessor sfp leds serial port (57600-8-n-1) ds3154 t3e3 transformer and network connections (t3e3) clocks and clock selection usb driver configuration power (5v) ethernet phy and connector redundant sonet optical sfp primary sonet optical sfp sfp leds ds33m33 spi config jumpers ethernet configuration jumpers ddr system side jumpers ds33m33-to-liu overhead fpga and test points a ddress databus test points comm select jumpers downloaded from: http:///
_________________________________________________________________________________________________ DS33M33DK rev: 102108 4 of 48 3. file locations this demo kit relies upon several supporting files, which ar e provided on the cd and are available as a zip file from the maxim website www.maxim-ic.com/DS33M33DK . all locations are given relative to the directory in the cd/zip file called ds33m33_def_ini_. table 3-1 shows the ds33m33, ds3154, and fp ga register definition files and configuration files. table 3-1. definition a nd configuration files file name file usage . \parallel_mode\ _ds33m_globalsonet.def top level definition file to select in chipviews register mode. this file will autoload the remaining definition files for the ds33m33 when parallel mode is used. (note the wan files still need to be loaded (either ds)). .\parallel_mode\ds3154dc.def .\parallel_mode\ds33m_bufferman.def .\parallel_mode\ds33m_encapdecap.def .\parallel_mode\ds33m_globaleth.def .\parallel_mode\ds33m_group.def .\parallel_mode\ds33m_lansubscriber.def .\parallel_mode\ds33m_port1.def .\parallel_mode\ds33m_port2.def .\parallel_mode\ds33m_port3.def .\parallel_mode\ds33m_serial_1234.def .\parallel_mode\ds33m_test.def .\parallel_mode\ds33m_vcat.def .\parallel_mode\overhead_fpga.def ds33m33 dependent files. these are called by _ds33m_globalsonet.def file, which is listed above. .\parallel_mode\m33_eos_vcg0_port2_port3_mii. mfg file for manually configuring the ds33m33 for eos vc3 with two ports assigned to vcg1. .\parallel_mode\m33_eos_vc3_mii100.mfg file for manually configuring the ds33m33 for eos vc3 mode. .\parallel_mode\m33_eopos_ds3.mfg file for manually configuring the ds33m33 for eopos ds3 mode. .\parallel_mode\enc_dec_lb.mfg encap/decap loopback/ .\parallel_mode\m30_rx_tx.mfg m30 mode rx and tx configuration. this file configures the mac for gmii mode and requires a gigabit ethernet link. .\parallel_mode\norm_ds3154_dlb.mfg .\parallel_mode\m33_pos_au3_liu.mfg two files for configuring the liu in m33 mmode and configuring the ds33m33 in pos au3 mode. .\ spi_mode.zip configuration mode files for spi? 3-wire bus mode. the default mode for this demo kit is parallel mode. to avoid accidental use the spi mode files have been provided in a zip format. .\ paritalconfig_ds33m_100mbit.mfg .\ paritalconfig_ds33m_gigabit.mfg files to change ethernet speed in the mac and global ethernet section. spi is a trademark of motorola, inc. downloaded from: http:///
_________________________________________________________________________________________________ DS33M33DK rev: 102108 5 of 48 4. basic operation note: in the following sections, software-related items are identified by bolding. text in bold refers to items directly from the ev kit software. text in bold and underlined refers to items from the windows operating system. 4.1 powering up the demo kit ? connect pcb power jack to the wall adapter. ? connect rs232 serial cable, or usb cable between the host pc and demo kit. ? verify that the jumpers are configured as described in table 5-1 . 4.1.1 general ? upon power-up the power leds (ds 30, ds31, ds32 green) will be lit. note that with ds33m3301a0 board revision, the led ds31 will be red wh en power conditions are correct. ? phy link led should be lit if an ethernet cable is connected. following are several basic system initializations. 4.2 basic ds33m33 initialization this section covers two basic methods for configuring the ds33m33. 1. device driver-based configurat ion: (note: the ds33m3302a0 board re vision does not come loaded with device drivers). if the pins j20.1+ j20.2 are jumpered the device driv er will auto configure the ds33m33 upon power-up. this enables traffic to pass from the ethernet port to the serial port. consult the device driver documentation for furt her details. to load the gui interface for the device drivers, go to the chipview register mode tools menu and select tools plugins ds33m30/m33 device driver demo . 2. register-based configuration: eos vc 3 with two ports assigned to vcg1. a. remove jumper j20.1+j20.2 to disable device drivers, and reset the board. b. launch chipview.exe and select register view . c. when prompted for a definition file, pick the file named _ds33m33_globalmicroport.def . several additional definition files will load. d. go to the file menu and select file memory config file load .mfg file . when prompted, select the file named m33_eos_vcg0_por t2_port3_mii.mfg . 4.2.1 additional configuration for ds33m33 ? using either a patch or crossover cable, connect the et hernet connector to an ordinary pc or network test equipment. this should cause the link led to turn on. ? place a loopback connector at the sonet network side; the optical los leds should go out. ? at this point any packets sent to the ds33m33 ar e echoed back. incoming packets (i.e., ping) should cause the activity led to blink. ? note that chipview.exe display settings can be changed using the options settings menu. 4.3 monitor and capture ethernet traffic ? although ping is mentioned, it is not the recommended frame source for testing. the ping command goes through the computers tcpip stack, and sometimes is not sent out the pcs netwo rk connector (i.e., if the pcs arp cache is out of date). additionally, ping requires two pcs, as a windows pc with only one adapter cannot ping itself (i.e., a local ping gets sent to local host instead of out the connector). with that said, ping is still a valuable test once the prototyping stage is complete. ? generation and capture of arbitrary (raw) packets can be accomplished using commview. a time-limited demo is available at www.ta mos.com/products/commview. ? wireshark (formerly ethereal) is a free packet captur e utility. download is availa ble at www.wireshark.org. ? adding additional ethernet ports to a pc is rather si mple when a usb-to-ethernet adapter is used. this allows for end-to-end testing using a single pc. w hen using two adapters, the pc has a different ip address for each adapter. test equipment allows select ion of either adapter. operating system-based downloaded from: http:///
_________________________________________________________________________________________________ DS33M33DK rev: 102108 6 of 48 network traffic is sent out the def ault adapter, which usually is the adapt er that has recently had connection to a live network. 5. jumpers and connectors jumpers and connectors are listed in table 5-1 . they are listed in order of appearance on the pcb from left to right, top to bottom (as viewed with sonet connectors port on the left side of the board). table 5-1. jumper s and connectors silkscreen reference function basic setting schematic page description j05 overhead test points j05.5+j05.6 jumpered 2 jumpers to connect overhead cpld to ds33m33. connector is marked to show that the odd numbered pins belong to the cpld. j02 spare connector not used 23 spare pins connected to overhead cpld. j08 overhead test points 2 jumpers to connect overhead cpld to ds33m33. connector is marked to show that the odd numbered pins belong to the cpld. jb01 (bottom of pcb) jtag 24 cpld jtag header. jumper p2+1 (low) p2+1 (low) 26 if auto negotiation is enabled, this setting advertises capability for 10/100/1000 speeds. if auto negotiation is disabled, then this setting forces 10mb mode. jumper p2+3 (high) p2+3 (high) 26 if auto negotiation is enabled this setting advertises capability for 10/100 speeds. if auto negotiation is disabled, this setting is not legal. jp05 + jp02 bias phy speed1 + speed0 jumper p2+3(high) p2+1 (low) 26 if auto negotiation is enabled, this setting advertises capability for 1000 speeds. if auto negotiation is disabled, this setting forces 1000mb mode. note: in gigabit mode the ds33m33 mac must be configur ed with indirect mac register maccr bit 15 set. jp03 bias phy anen jumper p2+3 (high) 26 jumper p2+3 to enable auto negotiation. jp04 bias phy duplex jumper p2+3 (high) 26 jumper p2+3 to enable full duplex; jumper p1.2 to force half duplex. jp06 bias phy manmdix jumper p2+1 (high) 26 default mdix setting p2+3 phy is set to straight mode; p2+1 phy is in crossover mode. jp07 bias phy nonieee jumper p2+3 (high) 26 jumper p2+3 to enable ieee compliant operation. jp08 bias phy multien jumper p2+1 (high) 26 phy advertisement setting. p2+3 selects multiple node priority (switch or hub); p1+2 selects single node priority (nic). jp09 bias phy mdixen jumper p2+1 (high) 26 p2+3 disables pair swap mode, p2+1 enables pair swap mode downloaded from: http:///
_________________________________________________________________________________________________ DS33M33DK rev: 102108 7 of 48 silkscreen reference function basic setting schematic page description jp10 bias phy macclken jumper p2+3 (low) 26 p2+3 phy clock to mac output is disabled, p1+2 phy clock to mac output is enabled. mac clock only needs to be enabled in gigabit mode. ds14 led activity 26 flashes for phy tx-rx activity. ds15 ds16 ds17 led link speed 1 of the 3 should be lit (when linked) 26 led to indicate link speedC1000, 100, or 10mbps. only one of the three leds should be lit. see jp05 + jp02 description for setting in gmii vs. mii mode. ds18 led duplex 25 led is on in full-duplex mode. jb03 jb02 phy test points 19 phy test points. the connector pinout is compatible with existing phy cards, but cannot be used with u04 on the board. j16 jtag jumper j16.1+j16.3 8 ds33m33 jtag. j20 runtime options na 1 currently the device drivers do not fit in flash, and are not loaded to the dk. j31 jtag 31 fpga jtag. jp25 jp26 comm port jumper p1+2 p1+2 15 jumper pins 1+2 to select the rs232 transceiver. jumper pins 2+3 to select the usb to serial converter. sw01 reset 11 system reset button. j21 test points 8 databus test points, pins d0Cd15 j24 test points 8 address bus test points pins a0C a13. j23 test points 8 test points for ds33m33 cs, wr rd, and int. jp22 jp21 jp20 spi bias swap cpha cpol jumper p1+2 8 jumper pins 2+1 to connect to processor parallel databus. leave jumper off to pull pin low, jumper pins 2+3 to pull pin high. jp14 jp13 jp12 jp11 spi connection cs miso mosi sck jumper p1+2 8 jumper pins 2+1 to connect to parallel databus. jumper pins 2+3 to connect to spi port. j30 pin bias ifsel_size ifsel_style spisel hiz dcesel rmiisel ale jumper ifsel_style hiz_n (parallel mode) 8 jumper to pull high, leave jumper off to pull low. j19 clock select jumper p2+4 6 clock selection for phy and ethernet side of ds33m33. jp01 clock select jumper p1+2 6 clad clock selection, jumper p1+2 to drive with 19.44mhz. jumper p2+3 to drive with 77.76mhz clock. downloaded from: http:///
_________________________________________________________________________________________________ DS33M33DK rev: 102108 8 of 48 silkscreen reference function basic setting schematic page description j09 j10 serdes analog test points 3, 4 test points to view analog +- differential serdes signals. to loopback ds33m33 tx rx remove the sfp and jumper p3+5 and p2+6. j03 j04 sfp test points jumper p9+10 3 test points for sfp module. ds02 ds03 sfp mod0 3 lit when a sfp module is installed. ds08 ds09 sfp txdisable 3 lit when tx is enabled. ds05 ds04 sfp los 3 lit when fiber optic cable is removed. j06 j07 sfp los / m33 los jumper p2+3 3, 4 jumper p2+3 to connect sfp los to ds33m33 los. jumper p2+4 to pull ds33m33 high. jumper p2+6 to pull ds33m33 low. u03 sfp installed 3, 4 primary sfp module. u02 sfp not installed 3, 4 redundant sfp module. j33 software debug 15 once ebdi. j32 jtag 20 liu jtag. j13 j15 j18 rclk rneg rpos jumpered 9 liu-to-ds33m33 connections. j13 j15 j18 tclk tneg tpos jumpered 9 liu-to-ds33m33 connections. jp16 jp23 jp24 liu port clocks not used 9 jumper 1+2 to drive tclkn with oscsel. jumper 2+3 to drive tclkn with rclkn. j22 j25 j26 j27 jb05 jb06 j28 j29 rx3 tx3 rx1 tx1 rx4 (bottom of pcb) tx4 (bottom of pcb) rx2 tx2 8 rx tx jumpers. jp17 liu_t3mclk jumper p2+3 20 jumper p2+3 to drive with t3 osc. jumper p1+2 to drive with t3_mclk_io. jp18 liu_alt_mclk jumper p2+3 20 jumper p2+3 to drive with osc sel. jumper p1+2 to drive with alternate mclk. jp19 liu_e3mclk jumper p2+3 20 jumper p2+3 to drive with e3 osc. jumper p1+2 to drive with e3_mclk_io. jp15 osc select jumper p2+3 20 jumper p2+3 to drive with t3 osc. jumper p1+2 to drive with e3 osc. downloaded from: http:///
___________________________________________________ ______________________________________________ ds3 3 m 3 3 dk rev: 102108 9 of 48 6 . line -side conne c t ions the DS33M33DK has two optical ports: one ethernet port and three t3e3 ports. 7 . syst e m conne c t ors system-side signals can be accessed from test point headers. the headers are clearly labeled with signal information. 8 . m ic roc ont rolle r the microcontroller has factory-installed firmware in on-c hip nonvolatile memory. this firmware translates memory access requests from the rs-232 serial port into register accesses on the ds33m33 and the fpgas. 9 . pow e r-supply conne c t ors connect a 5.0v wall adapter to the pcb power jack. led ds1 provides indications that a 5.0v supply is connected properly. the board power supplies (3.3v, 2.5v, and 1.8v ) are regulated to supply proper voltages to various circuits on the board. 1 0 . conne c t ing t o a com put e r both usb and serial modes are supported. to connect through a rs-232 serial port, set jumpers jp25 and jp26 jumpers to pins 1+2, identified in the silkscreen as uart,proc. connect a standard db-9 serial cable between the serial port on the DS33M33DK and an available serial port on the host computer. the host computer must be a windows-based pc. be sure the cable is a standard straight-throu gh cable rather than a null-modem cable. null-modem cables prevent proper operation. to connect through usb, set jumpers jp25 and jp26 jump ers to pins 3+2, identified in the silkscreen as usb,proc. connect a usb cable between the DS33M33DK usb connector and the pc. the host computer must be a windows-based pc, which should automatically recognize the device as a virtual com port and assign the device drivers. if drivers are not automatically assigned, direct the new hardware wizard to the driver files on the cd in the folder marked usbdrivers_cp210x . downloaded from: http:///
_________________________________________________________________________________________________ DS33M33DK rev: 102108 10 of 48 11. installing and running the software chipview is a general-purpose program that supports a number of maxim demo kits. to install the chipview software, run chipview.msi from the disk included in t he DS33M33DK box or from the zip file downloadable on our website at www.maxim-ic.com/DS33M33DK . after installation, run the chipview program with the DS33M33DK board powered up and connected to the pc. if the default installation options were used, one easy way to run chipview is to click the start button on the windows toolbar and select programs chipview chipview . in the opening screen, click the register view button. select the correct serial port in the port selection dialog box, then click ok . next, the definition file assignment window appears. this window has subwindows to select definition files for up to four separate boards on other maxim evaluation platforms. in the active subwindow, select the _ds33m_globalsonet.def definition file from the list shown, or browse to find it in another directory. press the continue button. after selecting the definition file, the main part of the chipview window displays the ds33m33s register map. to select a register, click on it in the register map. when a r egister is selected, the full name of the register and its bit map are displayed at the bottom of the chipview window. bits that are logic 0 are displayed in white, while bits that are logic 1 are displayed in green. the chipview software supports the following actions: ? toggle a bit. select the register in the register m ap and then click the bit in the bit map. ? write a register. select the register, click the write button, and enter the value to be written. ? write all registers. click the write all button and enter the value to be written. ? read a register. select the register in the register map and click the read button. ? read all registers. click the read all button. downloaded from: http:///
_________________________________________________________________________________________________ DS33M33DK rev: 102108 11 of 48 12. address map address space begins at 0x81000000. all offsets given in the following tables are relative to 0x81000000. registers in the fpga can be easily modified using the chipview host-based user interface software along with the definition file named overhead_fpga.def . table 12-1. address map offset device description 0x6000 fpga overhead cpld and clock/signal routing 0x4000 ds3154 ds3154 line interface unit 0x0000 ds33m33 ds33m33 registers 12.1 overhead cpld register map table 12-2. register map for overh ead cpld (reference designator u01) offset register name type description 0x0001 atoh_cfg control atoh configuration 0x0002 atohen_cfg control atohen configuration 0x0003 gpioawr control gpio a output enable + write value 0x0004 gpiobwr control gpio b output enable + write value 0x0005 dtoh_stat read-only dtoh status 0x0006 dtoh_sel control dtoh configuration 0x0007 gpiord_stat read-only gpio read values 0x0008 rdoh_stat read-o only rdoh status 0x000a rdoh_sel control rdoh select 0x000d taoh_cfg control taoh configuration 0x000f taohen_cfg control taohen configuration downloaded from: http:///
_________________________________________________________________________________________________ DS33M33DK rev: 102108 12 of 48 12.2 control and status registers register name: atoh_cfg register description: atoh configuration register offset: 0x0001 bit # 7 6 5 4 3 2 1 0 n a m e default 0 0 0 0 0 0 0 0 this register sets the overhead transport data byte value, which is positioned by the following register, atohen_cfg. register name: atohen_cfg register description: atohen configuration register offset: 0x0002 bit # 7 6 5 4 3 2 1 0 n a m e default 0 0 0 0 0 0 0 0 byte enable for overhead transport byte, the data value in atoh_cfg is positioned in the overhead as specified by atohen_cfg . examples follow: atohen_cfg atoh_cfg result 0 na data is not written onto the overhead when atohen_cfg = 0. 0x01 0x54 data value 0x54 is written onto t he first byte of the transport overhead. 0x81 0x54 data value 0x54 is written onto t he last byte of the transport overhead. 0x## 0xnn data value 0xnn is written to t he 0x## byte of the transport overhead. downloaded from: http:///
_________________________________________________________________________________________________ DS33M33DK rev: 102108 13 of 48 register name: gpioawr register description: gpio a output enable + write value register offset: 0x0003 bit # 7 6 5 4 3 2 1 0 name gpioa3 output en gpioa3 value gpioa2 output en gpioa2 value gpioa1 output en gpioa1 value default 0 0 0 0 0 0 0 0 bits 5 and 4: ds33m33 gpioa_3 three-state and level 0x = fpga three-states gpioa_3 pin 00 = fpga drives gpioa_3 pin with 0.0v 01 = fpga drives gpioa_3 pin with 3.3v bits 3 and 2: ds33m33 gpioa_2 three-state and level 0x = fpga three-states gpioa_2 pin 00 = fpga drives gpioa_2 pin with 0.0v 01 = fpga drives gpioa_2 pin with 3.3v bits 1 and 0: ds33m33 gpioa_1 three-state and level 0x = fpga three-states gpioa_1 pin 00 = fpga drives gpioa_1 pin with 0.0v 01 = fpga drives gpioa_1 pin with 3.3v register name: gpiobwr register description: gpio b output enable + write value register offset: 0x0004 bit # 7 6 5 4 3 2 1 0 name gpiob3 output en gpiob3 value gpiob2 output en gpiob2 value gpiob1 output en gpiob1 value default 0 0 0 0 0 0 0 0 bits 5 and 4: ds33m33 gpiob_3 three-state and level control 0x = fpga three-states gpiob_3 pin 00 = fpga drives gpiob_3 pin with 0.0v 01 = fpga drives gpiob_3 pin with 3.3v bits 3 and 2: ds33m33 gpiob_2 three-state and level control 0x = fpga three-states gpiob_2 pin 00 = fpga drives gpiob_2 pin with 0.0v 01 = fpga drives gpiob_2 pin with 3.3v bits 1 and 0: ds33m33 gpiob_1 three-state and level control 0x = fpga three-states gpiob_1 pin 00 = fpga drives gpiob_1 pin with 0.0v 01 = fpga drives gpiob_1 pin with 3.3v downloaded from: http:///
_________________________________________________________________________________________________ DS33M33DK rev: 102108 14 of 48 register name: dtoh_stat register description: dtoh status register offset: 0x0005 bit # 7 6 5 4 3 2 1 0 name stat7 stat6 stat5 stat4 stat3 stat2 stat1 stat0 default 0 0 0 0 0 0 0 0 read value of 1 of 81 bytes selected by dtoh_sel. register name: dtoh_sel register description: dtoh configuration register offset: 0x0006 bit # 7 6 5 4 3 2 1 0 name sel7 sel6 sel5 sel4 sel3 sel2 sel1 sel0 default 0 0 0 0 0 0 0 0 byte select for overhead transport byte, the overhead byte specified by dtoh_cfg is written to dtoh_stat . examples: dtoh_sel dtoh_stat result 0 first byte the first byte of the trans port overhead is written to dtoh_stat. 0x80 last byte the last byte of the trans port overhead is written to dtoh_stat. register name: gpiord_stat register description: gpio read values register offset: 0x0007 bit # 7 6 5 4 3 2 1 0 name gpioa3 gpioa2 gpioa1 gpiob3 gpiob2 gpiob1 default 0 0 0 0 0 0 0 0 bit 6: ds33m33 gpioa3 pin value reflects the value of ds33m33 gpioa3 pin. bit 5: ds33m33 gpioa3 pin value reflects the value of ds33m33 gpioa2 pin. bit 4: ds33m33 gpioa3 pin value reflects the value of ds33m33 gpioa1 pin. bit 2: ds33m33 gpioa3 pin value reflects the value of ds33m33 gpiob3 pin. bit 1: ds33m33 gpioa3 pin value reflects the value of ds33m33 gpiob2 pin. bit 0: ds33m33 gpioa3 pin value reflects the value of ds33m33 gpiob1 pin. downloaded from: http:///
_________________________________________________________________________________________________ DS33M33DK rev: 102108 15 of 48 register name: rdoh_stat register description: rdoh status register offset: 0x0008 bit # 7 6 5 4 3 2 1 0 name default 0 0 0 0 0 0 0 0 read value from the member and byte sele cted by rdoh_sel[7:4] and rdoh_sel[3:0] register name: rdoh_sel register description: rdoh select register offset: 0x000a bit # 7 6 5 4 3 2 1 0 name if3 if2 if1 if0 b3 b2 b1 b0 default 0 0 0 0 0 0 0 0 bits 7 to 4: overhead interface member select. writing if[3:0] to a value of 0 disables. writing 1 to 10 selects among the 10 members used in rdoh_stat. bits 3 to 0: byte select. writing b[3:0] to a value of 0-to-n select s the nth byte in the member selected. register name: taoh_cfg register description: taoh configuration register offset: 0x000d bit # 7 6 5 4 3 2 1 0 name rclk8 rclk7 rclk6 rclk5 rclk4 rclk3 rclk2 rclk1 default 0 0 0 0 0 0 0 0 value to be written to the member and byte selected by taohen_cfg[7:4] and taohen_cfg [3:0] register name: taohen_cfg register description: taoh enable configuration register offset: 0x000f bit # 7 6 5 4 3 2 1 0 name if3 if2 if1 if0 b3 b2 b1 b0 default 0 0 0 0 0 0 0 0 bits 7 to 4: overhead interface member select. writing if[3:0] to a value of 0 disables. writing 1 to 10 selects among the 10 members used in taoh_stat. bits 3 to 0: byte select. writing b[3:0] to a value of 0-to-n sele cts the nth byte in the member selected. downloaded from: http:///
_________________________________________________________________________________________________ DS33M33DK rev: 102108 16 of 48 13. additional information/resources 13.1 ds33m33 information for more information about the ds33m33, refer to the ds33m33 data sheet at www.maxim-ic.com/ds33m33 . 13.2 DS33M33DK information for more information about the DS33M33DK, re fer to the DS33M33DK quick view page at www.maxim-ic.com/DS33M33DK . 13.3 technical support for additional technical support, submit your questions at www.maxim-ic.com/support . downloaded from: http:///
_________________________________________________________________________________________________ DS33M33DK rev: 102108 17 of 48 14. component list designation qty description supplier part c08, cb34, cb36, cb37, cb38, cb39, cb40, cb41, cb42, cb58, cb64, cb66, cb67, cb68, cb72, cb79, cb92, cb101, cb104, cb112, cb170 21 l_0603 ceram .01uf 50v 10% x7r avx 06035c103kat see next row (begins with c02) 61 l_0603 ceram .1uf 16v 20% x7r avx 0603yc104mat c02, c04, c05, c07, c10, c15, c 18, cb05, cb06, cb09, cb10, cb11, cb12, cb16, cb21, cb22, cb23, cb25, cb28, cb33, cb43, cb44, cb45, cb47, cb53, cb54, cb63, cb65, cb69, cb77, cb83, cb85, cb88, cb89, cb94, cb95, cb97, cb98, cb113, cb115, cb116, cb118, cb122, cb126, cb128, cb134, cb135, cb 137, cb138, cb140, cb142, cb143, cb144, cb146, cb148, cb156, cb160, cb168, cb177, cb186, cb187 db01 1 schottky diode, 1 amp 40 volt international rectifier 10bq040 ds01, ds06, ds07, ds10, ds11, ds12, ds13, ds31 8 led, red/green, smd liteon 160-1172-1-nd gnd_tp01, gnd_tp02, gnd_tp03, gnd_tp04, gnd_tp11, gnd_tpb01, gnd_tpb02, gnd_tpb03, gnd_tpb06 9 standard ground clip keystone 4954 ds14, ds15, ds16, ds17 4 led, green/green, smd lumex 67-1362-1-nd j34 1 l_conn, db9 ra, long case amp 747459-1 ub02, ub04, ub06 3 spi serial eeprom 2m 8 pin soic 2.7v to 3.6v atmel at25f2048n- 10su-2.7 rpb24, rpb26 2 resistor, 4 pack, 50 ohm 2pct quad 0603 koa cn1j4ttd500g u10 1 ic, single-chip usb to uart bridge, 28 pin qfn sil cp2101 j32 1 l_terminal strip, 10 pin, dual row, vert do not populate dnp dnp u04 1 gig phyter v, 10/100/1000 ethernet physical layer, 128 pin qfp national semiconductor dp83865dvh u07 1 quad ds3/e3/sts1 liu 144p bga maxim ds3154 u05 1 ic, ethernet over sdh/sonet (eos), -40c to 85c, 256-pin csbga maxim ds33m33n xb01 1 xtal low profile 8.0mhz ecl ec1-8.000m see next row (begins with c01) 79 0603 ceram 4.7uf 6.3v multilayer digi-key ecj-1vb0j475m c01, c03, c06, c09, c11, c12, c13, c14, c16, c23, cb03, cb04, cb07, cb 14, cb15, cb17, cb18, cb19, cb20, cb24, cb26, cb27, cb29, cb30, cb31, cb32, cb46, cb49, cb55, cb60, cb62, cb70, cb73, cb74, cb75, cb76, cb78, cb82, cb84, cb86, cb90, cb91, cb93, cb96, cb100, cb102, cb 103, cb106, cb107, cb109, cb 110, cb114, cb117, cb119, cb120, cb121, cb123, cb127, cb129, cb 131, cb132, cb133, cb136, cb139, cb141, cb147, cb150, cb153, cb154, cb162, cb163, cb165, cb167, cb173, cb175, cb181, cb182, cb183, cb190 see next row (begins with cb50) 20 0603 ceram .1uf 16v 10% panasonic ecj-1vb1c104k downloaded from: http:///
_________________________________________________________________________________________________ DS33M33DK rev: 102108 18 of 48 cb50, cb56, cb57, cb61, cb71, cb80, cb81, cb87, cb99, cb105, cb108, cb149, cb151, cb152, cb155, cb161, cb166, cb172, cb179, cb180 see next row (begins with c17) 21 1206 ceram 10uf 10v 20% panasonic ecj-3yb1a106m c17, c19, c20, c21, c22, c24, cb 188 , cb01, cb02, cb08, cb13, cb35, cb48, cb51, cb52, cb59, cb111, cb124, cb125, cb130, cb169 cb164, cb184 2 l_1206 ceram 1uf 16v 10% panasonic ecj-3yb1c105k cb178 1 1206 ceram 4.7uf 25v 10% x5r panasonic ecj-3yb1e475k cb158, cb159, cb185, cb189 4 l_d case tant 68uf 16v 20% panasonic ecs-t1cd686r rb09, rb10 2 res 0603 100 ohm 1/16w 1% panasonic erj-3ekf1000v rb12, rb13 2 res 0603 1.00k ohm 1/16w 1% panasonic erj-3ekf1001v rb17, rb19, rb20, rb21, rb22, rb23, rb24, rb25 8 res 0603 332 ohm 1/16w 1% panasonic erj-3ekf3320v rb16 1 res 0603 9.76k ohm 1/16w 1% panasonic erj-3ekf9761v r02, r04, r05, rb04, rb27 5 res 0603 0.0 ohm 1/16w 5% panasonic erj-3gey0r00v rb01, rb02, rb29 , rb05 4 l_res 0603 10k ohm 1/16w 5% panasonic erj-3geyj103v r03 1 res 0603 1.0m ohm 1/16w 5% panasonic erj-3geyj105v r01, rb06, rb11 3 res 0603 2.0k ohm 1/16w 5% panasonic erj-3geyj202v rb08 1 res 0603 2.2k ohm 1/16w 5% panasonic erj-3geyj222v rb14, rb15 2 res 0603 30 ohm 1/16w 5% panasonic erj-3geyj300v rb07, rb26 , rb28, rb30 4 res 0603 33 0 ohm 1/16w 5% panasonic erj-3geyj331v rb03, rb18 2 res 0805 10k ohm 1/10w 1% panasonic erj-6enf1002v sw01 1 switch mom 4pin sing le pole panasonic evqpae04m rpb18 1 resistor, 4 pack, 100 ohm 5pct quad 0603 panasonic exb-v8v101jx rpb01, rpb02, rpb05, rpb14, rpb20, rpb30, rpb36, rpb48, rpb52 9 resistor, 4 pack, 1k ohm 5pct quad 0603 panasonic exb-v8v102jx rpb03, rpb08, rpb10, rpb11, rpb12, rpb13, rpb29, rpb32, rpb33, rpb40, rpb41, rpb43, rpb45, rpb47, rpb49, rpb50, rpb51, rpb54, rpb55, rpb56, rpb57, rpb58, rpb60, rpb61, rpb62, rpb63, rpb64 27 resistor, 4 pack, 10k ohm 5pct quad 0603 panasonic exb-v8v103jx rpb19, rpb21, rpb28 3 resistor, 4 pack, 2.2k ohm 5pct quad 0603 panasonic exb-v8v222jx rp02, rp03, rp04, rp05, rp06, rp07, rp08, rp09, rp10, rp11, rp12, rp13, rpb15, rpb16, rpb17, rpb23, rpb25, rpb27, rpb31, rpb34, rpb35, rpb37, rpb44 23 resistor, 4 pack, 30 ohm 5pct quad 0603 panasonic exb-v8v300jx rp01, rpb04, rpb06, rpb07, rpb09, rpb22, rpb38, rpb39, rpb42, rpb46, rpb53, rpb59 12 resistor, 4 pack, 330 ohm 5pct quad 0603 panasonic exb-v8v331jx l01, l02, lb01, lb02, lb03, lb04 6 1uh 10% 0805 multilayer ceramic 400 ma tdk glf2012t1r0m downloaded from: http:///
_________________________________________________________________________________________________ DS33M33DK rev: 102108 19 of 48 j01, j30 2 header, 14 pin, dual row, vert samtec hdr-tsw-107-14- t-d j11 1 connector, single level, gigabit rj-45, 10 pin halo electronics hfj11-1g02e u08 1 ic, fpga, 1.2v, 20x20 tqfp, 144 pin lat lfe2-6e-5tn144c u01 1 ic, fpga, 1.2v, 20x20 tqfp, 144 pin lat lfec3e-3t144c ds04, ds05, ds28 , ds19, ds20, ds21, ds22, ds23, ds24, ds25, ds26, ds27 12 l_led, red, smd panasonic ln1251c ds02, ds03, ds08, ds09, ds29 , ds18, ds30, ds32 8 l_led, green, smd panasonic ln1351c ub09 1 ic, linear reg 1.5w, 1.8v or adj, 1a, 16tssop-ep maxim max1793eue-18 ub08 1 ic, linear reg 1.5w, 2.5v or adj, 1a, 16tssop-ep maxim max1793eue-25 ub10, ub11, ub13 3 ic, linear reg 1.5w, 3.3v or adj, 1a, 16tssop-ep maxim max1793eue-33 ub01, ub03 2 ic, ldo regulator with reset,1.20v output 300 ma, 6 pin sot23 maxim max1963ezt120-t ub07 1 microprocessor voltage monitor, 3.08v reset, 4pin sot143 maxim max811teus-t u09 1 mmc2107 processor motorola mmc2107 j03, j04, j23 3 terminal strip, 10 pin, dual row, vert digi-key s2012-05-nd j33 1 100 mil 2*7 pos jumper na na j35 1 type b single rt angle, black digi-key wm17108-nd jb08 1 100 mil 2 pos jumper na na see next row (begins with jp01) 27 100 mil 3 pos jumper na na jp01, jp02, jp03, jp04, jp05, jp06, jp 07, jp08, jp09, jp10, jp11, jp12, jp13, jp14, jp15, jp16, jp17, jp18, jp19, jp20, jp21, jp22, jp23, jp24, jp25, jp26, jpb01 tpb01, tpb02, tpb03 3 test point, 1 plated hole, do not stuff na na u06 1 double data rate (ddr) sdram 2-2-2 timing 256mbitx16 tssop micron mt46v16m16tg- 75e u11, u12 2 cypress sram 4mbit*8 cypress cy62148dv30l- 70sxi ub14 1 dual rs-232 transceivers with 3.3v/5v internal capacitors maxim max3233e jb02 1 test points for smd 50 pin, 2 row vertical na na_notpopulat ed ub05 , ub12 2 high speed inverter fairchild nc7sz86 j24 1 non populated header, 14 pin, dual row, vert samtec nopop-hdr-tsw- 107-14-t-d jb05, jb06 2 do not populate l_2 pin header, .100 centers, vertical samtec nopop-tsw-102- 07-t-s j09, j10 2 terminal strip, 6 pin, dual row, vert not populated samtec nopop-tsw-103- 07-t-d j21 1 nopop terminal strip, 16 pin, dual row, vert samtec nopop-tsw-108- 07-t-d yb04 1 oscillator, crystal clock, 5.0v - 34.368 mhz saronix nth089aa-34.368 yb05 1 socketed oscillator, crystal clock, 3.3v - 25.000 mhz saronix nth089aa3- 25.000+socket yb03 1 oscillator, crystal clock, 3.3v - 44.736 mhz saronix nth089aa3-44.736 downloaded from: http:///
_________________________________________________________________________________________________ DS33M33DK rev: 102108 20 of 48 jb09 1 conn 2.1mm/5.5mm pwrjack rt angle pcb, closed frame, high current 24vdc@5a also requires 5v acdc adapter input 100-240vac 50-60hz 0.6a output dc 5v 2.6a. pn dms050260-p5p-sz. model 3z- 161wp05 cui, inc pj-002ah jb03 1 plug, smd, 50 pin, 2 row vertical samtec sfm-125-l2-s-d-lc u02, u03 2 sfp host / receptacle parts_kit sfp_host-tyco hb01, hb02, hb03, hb04, hb05 5 rub ber bumper 0.5 inch na sj5518-0 yb01 1 oscillator, crystal clock, 3.3v - 19.44 mhz saronix socket+nth089a 3-19.44 yb02 1 oscillator, crystal clock, 3.3v - 77.76 mhz saronix socket+nth089a 3-77.7600 t01 1 xfmr, octal t3/e3, 1 to 2, smt 32 pin pulse t3049 cb145, cb157, cb171, cb174, cb176 5 d case tant 470uf 6.3v 20% kem t491d477m006as j22, j25, j26, j27, j28, j29 6 l_2 pin header, .100 centers, vertical samtec tsw-102-07-t-s j06, j07, j12, j13, j14, j15, j17, j18, j19, j20, jb04, jb07 12 terminal strip, 6 pin, dual row, vert samtec tsw-103-07-t-d j16, j31, jb01 3 l_terminal strip, 10 pin, dual row, vert samtec tsw-105-07-t-d j02, j05, j08 3 terminal strip, 16 pin, dual row, vert samtec tsw-108-07-t-d downloaded from: http:///
_________________________________________________________________________________________________ DS33M33DK rev: 102108 21 of 21 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the ci rcuitry and specifications wi thout notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2008 maxim integrated products 15. schematics the DS33M33DK schematics are featured in the following page s. the schematic contains five hierarchal blocks: microcontroller, ds3154, ethernet phy, et hernet test points, and overhead cpld. all signals inside a hierarchy block are local, with exception for v cc and ground. in-port and out-port connectors are used to allow signals inside a hierarchy block to become accessible as pins on the hierarchy blocks symbol. from here blocks are wired together as if they were ordinary components. figure 15-1 shows the system diagram in terms of hierarchal blocks with schematic page numbers given for each functional block. figure 15-1. ds33m33 pcb layout and schem atic hierarchy block page listing p block page 1 symbol schematic pages 13-18 ds3154 liu block page 9 symbol schematic pages 20-22 overhead cpld page 10 symbol schematic pages 23-24 ds33m33 schematic pages 1-10 power supply schematic pages 11-12 ethernet phy page 6 symbol schematic pages 19, 25-26 sonet sfp pages 4-5 liu test points page 9 ddr page 7 clocks and configuration pages 6,8 is a registered trademark of maxim integrated products. downloaded from: http:///
beginning of DS33M33DK DS33M33DK contents / index addr<13..0> data<7..0> wr_rw rd_ds m3x_ale cpld_cs spi_miso spi_sck m3x_hiz_n n6 m3x_ifsel_style m3x_ifsel_size d6_spi_cpha d2_spi_clk data<15..0> 15 14 12 13 9 10 11 8 0 1 2 3 45 6 7 89 10 11 13 3 4 spi_ss te3_int phy_int reset_lan reset_sys 30 12 25mhzosc_to_proc d5_spi_swap d1_spi_mosi spi_mosi m3x_jtrst_n m3x_jtms m3x_jtclk m3x_jtdi m3x_spisel m3x_test_en m3x_mt0 m3x_mt1 m3x_mt2 m3x_int d7_spi_cpol reset_sys m3x_jtdo m3x_cladclk m3x_clkc m3x_clkb m3x_clka m3x_ale wr_rw rd_ds m3x_cs m3x_int j20 1 2 3 4 5 6 u05 l12 p13 m12 r13 n13 t13 r14 p14 t14 l13 r15 m13 n14 t15 n12 m3 l2 k2 l5 n8 n7 n9 n10 m9 m8 m7 m10 m11 l8 h11 h12 j11 l9 k12 b1 p7 n5 m4 n2 p2 n3 p1 n4 b2 a1 m2 m6 e14 c1 f5 m5 rpb34 4 3 2 1 5 6 7 8 d0_spi_miso n11 addr<13..0> te3_l_cs cs_x1 microport. p.1,13-18 DS33M33DK01a0 microport. p.1,13-18 ddr memory. p.7 oscillators. p.6 bias+config. p.8 cr-1 : @\_rc_lib\.\_rc_top_dn_\(sch_1):page1 ethernet. p.5-6,19,25-26 power. p.11-12 serdes. p.3-4 steve scully 1/26(total) 10/03/2007 1/12(block) block name: _rc_top_dn_. parent block: overhead. p.2,10,23-24 t3e3 liu i/f. p.2,9,20-22 8a2 8d4 8d4 8d7 8d3 13b7v 8d3 13b6v 8d3 13b6v 6b4 14d1v 6b4 16b3v 10b5 17c6v 9b1 10b4 11b3 1b5 13b6v 8c1 9c1 10b5 1d3 17c4v 9c1 17c6v 1b1 9c3 10b5 8b3 8c6 8d3 8d4 8d6 17a5v 17a6v 1a2 9c1 10b5 8b5 17a5v 17c4v 6a5 17c6v 8d7 8d4 13b7v 8a6 8a7 8a7 8a8 8a2 8a3 8a2 8a2 8a8 8b2 8b8 8b8 8b8 1d3 8c1 8a8 13b7v 8d7 9b1 10b4 11b3 1a8 13b6v 8a7 6c6 10b7 8b2 1d3 17c4v 6a7 10b7 9b2 10b7 9b2 10b7 8a2 8b2 1a8 17c4v 8c2 8d3 1a8 17c4v 8c1 1b8 8a8 13b7v 8d4 9c1 10b5 1a8 8b5 17a5v 17c4v page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 control ds33m33_u test hiz* mt0 mt1 mt2 ifsel[0] ifsel[1] refclk clkb clka clkc d[15] d[14] d[13] d[12] d[11] d[10] d[8] d[7]/cpol d[6]/cpha d[5]/spiswap d[4] d[3] d[1]/sdi d[2]/sclk ale int* cs* d[9] d[0]/sdo rd*/ds* wr*/r/w* spisel rst* jtdo jtdi jtclk jtms jtrst* a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] a[12] a[13] v3_3 26 5 4 3 1 conn_6p_u _motprocrescard_dn microprocessor hierarchy block ale_dut rd_ds misc_io<12..1> wr_rw en_source_time enable_drv spi_miso spi_sck spi_cs spi_mosi a_dut_<13..0> cs_x1 int2 d_dut<7..0> int3 int4 enable_clbk cs_x2 cs_x3 reset_in proc_oscin reset_out downloaded from: http:///
m3xoh_atoh m3xoh_atohsof m3xoh_atohclk cpld_atoh cpld_rdohvld cpld_atohsof cpld_atohclk cpld_dtoh cpld_dtohsof cpld_dtohclk cpld_atohen m3xoh_atohen m3xoh_taohen m3xoh_taohsof m3xoh_taohvld cpld_oh1 cpld_ohclk cpld_taohen cpld_taohsof cpld_taohvld cpld_rdoh cpld_rdohsof cpld_taoh m3xoh_taoh m3x_sfp2_rdn m3x_sfp1_rdn m3x_sfp2_tdn m3x_sfp1_tdp m3x_sfp1_tdn m3x_los1 m3x_los2 m3x_sfp2_tdp m3xoh_rdohsof m3xoh_rdoh m3xoh_rdohvld m3xoh_ohclk m3xoh_oh1 m3xoh_atoh m3xoh_taoh m3xoh_taohen m3xoh_atohen m3xoh_dtohsof m3xoh_dtoh m3xoh_dtohclk m3x_sfp2_rdp m3x_sfp1_rdp 30 30 30 100 100 30 100 .01uf .01uf .01uf .01uf 30 rb09 rb10 u05 f13 g13 g14 f14 f12 g12 b15 m16 f16 k13 m14 k16 d16 j12 h14 j13 l16 e16 h13 j14 j15 k14 p16 h16 n16 g16 rpb15 4 3 2 1 5 6 7 8 rpb16 4 3 2 1 5 6 7 8 rp04 4 3 2 1 5 6 7 8 rp03 4 3 2 1 5 6 7 8 rpb17 4 3 2 1 5 6 7 8 j08 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 j05 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 rpb18 4 3 2 1 5 6 7 8 cb34 cb37 cb36 cb40 steve scully 2/12(block) 10/03/2007 2/26(total) cr-2 : @\_rc_lib\.\_rc_top_dn_\(sch_1):page2 DS33M33DK01a0 overhead. p.2,10,23-24 t3e3 liu i/f. p.2,9,20-22 block name: _rc_top_dn_. 2a6 10c4 10b7 10c7 10c7 10c7 10c7 10c7 10c4 2a6 2a6 10c7 10c7 10c5 10b7 10b7 10c7 10c7 10c5 2a6 3c6 3b5 4c6 4b5 3c5 3d6 4c5 4d6 4c5 4d6 4b6 3b6 3c5 3d6 2b6 2c6 2c6 2b6 3d6 3b5 4c6 4b5 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 ds33m33_u overhead i/f transport overhead i/f sts-3 system i/f rdnb rdpb rdna rdpa tdnb tdpa taoh ohclk tdna oh1 taohsof taohen taohvld rdoh rdohsof rdohvld atoh atohen atohsof dtoh dtohsof dtohclk atohclk losa losb tdpb conn_16p 24 8 10 12 14 16 3 1 7 9 11 13 15 5 6 conn_16p 24 8 10 12 14 16 3 1 7 9 11 13 15 5 6 downloaded from: http:///
mod0 is grounded in the sfp pullups for open drain pins this subcircuit is for observation and loopback only not for production use place / route caps and testpoint such that they can removed without impact serves as device detect sfp2_rate sfp2_los sfp2_mod1 sfp2_tx_fault sfp2_mod2 sfp2_mod0 10k 10k m3x_sfp2_rdn m3x_sfp2_rdp m3x_sfp2_tdp .1uf 4.7uf 1uh 4.7uf 4.7uf .1uf 1uh 330 sfp2_i2c_clk sfp2_txdisable sfp2_vcct sfp2_vccr sfp2_tx_fault sfp2_i2c_sda sfp2_dev_detect sfp2_los sfp2_rate sfp2_mod0 sfp2_txdisable sfp2_mod2 sfp2_mod1 sfp2_los sfp2_dev_detect sfp2_i2c_clk sfp2_i2c_sda sfp2_vccr sfp2_tx_fault sfp2_vcct sfp2_rate m3x_sfp2_tdn m3x_sfp2_tdp m3x_sfp2_rdp m3x_sfp2_rdn .01uf .01uf m3x_sfp2_tdn 1k m3x_los2 sfp2_los sfp2_txdisable sfp2_los sfp2_mod0 red green green cb33 cb31 lb04 cb32 cb24 cb23 lb02 j03 1 2 3 4 5 6 7 8 9 10 u02 21 22 23 24 25 26 27 28 29 30 31 8 6 5 4 7 12 13 19 18 3 2 15 16 14 10 9 11 1 20 17 ds02 1 2 rpb09 4 3 2 1 5 6 7 8 ds08 1 2 ds05 1 2 rpb11 4 3 2 1 5 6 7 8 rpb12 4 3 2 1 5 6 7 8 cb42 j09 1 2 3 4 5 6 cb39 j06 1 2 3 4 5 6 rpb14 4 3 2 1 5 6 7 8 steve scully DS33M33DK01a0 3/12(block) 10/03/2007 3/26(total) cr-3 : @\_rc_lib\.\_rc_top_dn_\(sch_1):page3 serdes. p.3-4 block name: _rc_top_dn_. 3b2 3a1 3b7 3b2 3a5 3a1 3b3 3c2 3a3 3c3 3b3 3a5 2b2 3c6 2b2 3d6 3d6 2b2 3b2 3c2 3a5 3d2 3d3 3a7 3c2 3c2 3b1 3b7 3a7 3a5 3a1 3a7 3a1 3a7 3a5 3a5 3a3 3a7 3a7 3b7 3b2 3a7 3a5 3a3 3a3 3a3 3b5 3a7 3a3 3b5 3b2 3a7 3c5 2c2 3c5 2b2 2b2 3b5 2b2 3b5 3d6 2c2 2b2 3b2 3a7 3a5 3a1 3c2 3a3 3b7 3b2 3a7 3a1 3b3 3a7 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 26 5 4 3 1 conn_6p_u v3_3 26 5 4 3 1 conn_6p_u v3_3 v3_3 sfp_host cgnd cgnd cgnd cgnd cgnd cgnd cgnd cgnd cgnd cgnd cgnd veer rd- rd+ vcct vccr veer td+ veet veet td- veer veer los rate mod-def1 mod-def0 mod-def2 tx_disable tx_fault veet v3_3 6 10 8 4 1 2 3 5 7 9 conn_10p downloaded from: http:///
pullups for open drain pins this subcircuit is for observation and loopback only not for production use place / route caps and testpoint such that they can removed without impact mod0 is grounded in the sfp serves as device detect sfp1_mod2 sfp1_mod1 sfp1_vccr m3x_sfp1_rdn .1uf 4.7uf 1uh 4.7uf 4.7uf 1uh 330 sfp1_rate sfp1_los sfp1_vcct sfp1_vccr sfp1_i2c_sda sfp1_txdisable sfp1_i2c_clk sfp1_tx_fault sfp1_dev_detect .1uf sfp1_dev_detect sfp1_i2c_clk sfp1_i2c_sda sfp1_tx_fault sfp1_txdisable sfp1_mod2 sfp1_mod0 sfp1_mod1 sfp1_rate sfp1_los m3x_sfp1_tdn m3x_sfp1_tdp m3x_sfp1_rdp m3x_sfp1_rdn .01uf .01uf m3x_sfp1_tdp m3x_sfp1_tdn m3x_sfp1_rdp 10k 10k sfp1_mod0 sfp1_rate sfp1_los sfp1_tx_fault 1k m3x_los1 sfp1_los sfp1_los sfp1_txdisable sfp1_mod0 green green red sfp1_vcct cb22 cb29 j04 1 2 3 4 5 6 7 8 9 10 lb03 cb17 cb30 cb16 lb01 u03 21 22 23 24 25 26 27 28 29 30 31 8 6 5 4 7 12 13 19 18 3 2 15 16 14 10 9 11 1 20 17 rpb06 4 3 2 1 5 6 7 8 ds03 1 2 ds09 1 2 ds04 1 2 rpb01 4 3 2 1 5 6 7 8 rpb10 4 3 2 1 5 6 7 8 rpb03 4 3 2 1 5 6 7 8 cb41 j10 1 2 3 4 5 6 cb38 j07 1 2 3 4 5 6 10/03/2007 steve scully 4/12(block) 4/26(total) DS33M33DK01a0 cr-4 : @\_rc_lib\.\_rc_top_dn_\(sch_1):page4 serdes. p.3-4 block name: _rc_top_dn_. 4c3 4b3 4d3 2c2 4b5 4b2 4a7 4b7 4b2 4a7 4a5 4b5 4b5 4c2 4c2 4a5 4b2 4a7 4c2 4b1 4a3 4a3 4a3 4a7 4a3 4a5 4a3 4a7 4a7 4a5 4a7 4a7 4a1 4b7 4a7 4a5 4a1 4d6 2c2 4d6 2c2 2c2 4c6 2c2 4c6 4c5 2c2 4c5 2c2 2c2 4b5 4b3 4a5 4b2 4a1 4b7 4b2 4a5 4a1 4c2 4a3 2b2 4b2 4a7 4a5 4a1 4b7 4b2 4a7 4a1 4c2 4a3 4b3 4a7 4d2 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 26 5 4 3 1 conn_6p_u 26 5 4 3 1 conn_6p_u v3_3 v3_3 v3_3 sfp_host cgnd cgnd cgnd cgnd cgnd cgnd cgnd cgnd cgnd cgnd cgnd veer rd- rd+ vcct vccr veer td+ veet veet td- veer veer los rate mod-def1 mod-def0 mod-def2 tx_disable tx_fault veet v3_3 v3_3 6 10 8 4 1 2 3 5 7 9 conn_10p downloaded from: http:///
30 eth_rx_err eth_rxd<7..0> 0 1 2 3 4 5 6 7 eth_txd<7..0> 0 1 2 3 30 4 5 6 7 30 30 gtxclk m3x_lan_clko m3x_lan_clk m3x_rmiisel m3x_dcesel eth_rx_crs eth_col_det eth_mdio eth_mdc eth_tx_en eth_tx_clk gmii_tx_er_ eth_rxdv eth_rx_clk rp08 4 3 2 1 5 6 7 8 rpb27 4 3 1 5 6 7 8 rp10 4 3 2 1 5 6 7 8 r7 t7 p11 t5 t3 t2 p12 r12 t12 t8 r8 p8 t9 r9 p9 t10 r10 p10 r11 t11 t6 r3 p4 r4 t4 p5 r5 p6 r6 p3 rp11 4 3 2 1 5 6 7 8 r2 2 u05 10/03/2007 5/26(total) 5/12(block) cr-5 : @\_rc_lib\.\_rc_top_dn_\(sch_1):page5 DS33M33DK01a0 steve scully ethernet. p.5-6,19,25-26 block name: _rc_top_dn_. 6c4 6c3 6d3 6c3 6c4 6a1 6c4 6a7 6a5 8b2 8b2 6d4 6d4 6b4 6b4 6c3 6c3 6b1 6c4 6d4 6d3 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 ds33m33_u ethernet mac i/f lanclko txd[1] txd[3] txd[2] txd[4] txd[6] txd[5] rxd[1] rxd[0] rxd[4] rxd[2] rxd[3] rxd[5] rxd[7] rxd[6] txd[7] txd[0] rxclk rxerr rxdv txen txerr txclk crs col dcesel mdc mdio rmisel gtxclk lanclki downloaded from: http:///
used in rmii mode (50 mhz) eth_ref_clk is only clka and clkb testpoints are in the liu block refclk & clkc testpoints are in the phy block clock testpoints: not connection to a resource card is intended for use as testpoints ethernet connector (i.m. bus) 25mhzosc_to_proc eth_txd<7..0> clk_to_mac gtxclk eth_col_det eth_rxd<7..0> gmii_tx_er_ i23 i24 1uh 4.7uf .1uf m3x_cladclk_to_liu 30 i22 2.2k 30 30 25.000mhz_3.3v_socket clk_to_mac av_lan_clk py25mhzosc m3x_lan_clko m3x_clkc refc_25m jmp_3 m3x_cladclk gmii_tx_er_ 19.44mhz_3.3v_socket 4.7uf .1uf 77.76mhz_3.3v_socket clk_to_mac gtxclk av_lan_clk eth_rxd<7..4> eth_txd<7..4> reset_lan eth_rxd<3..0> eth_rx_clk eth_rxdv eth_rx_crs eth_rx_err eth_txd<3..0> eth_tx_clk eth_tx_en eth_mdio eth_mdc py25mhzosc phy_int m3x_lan_clk 30 rb08 yb02 4 5 1 8 jp01 1 3 2 rb15 rb14 yb01 4 5 1 8 yb05 4 5 1 8 j19 1 2 3 4 5 6 rp13 4 3 2 1 5 6 7 8 rpb23 4 3 2 1 5 6 7 8 l01 c01 c02 c03 c04 6/26(total) steve scully 6/12(block) 10/03/2007 cr-6 : @\_rc_lib\.\_rc_top_dn_\(sch_1):page6 DS33M33DK01a0 ethernet. p.5-6,19,25-26 block name: _rc_top_dn_. 6b1 25a7v 19b3v 25b1v 19b3v 6a7 25b7v 19b3v 6a1 5a4 19c3v 5a5 25a1v 6b1 5c6 9b2 25b1v 19b3v 6b1 6c3 5a4 19b3v 6b4 1a8 25b4v 6b4 5a4 10b7 1d2 10b7 1d3 25a7v 19b3v 6c4 5c6 25b7v 19b3v 5a4 6c4 25b1v 19b3v 6c3 6a7 6c4 5b6 19b3v 25b7v 5b2 6d3 19c3v 25b7v 5c3 19c3v 25a1v 5a5 19c3v 25a1v 5c3 19b3v 25a1v 6c4 5b6 19c3v 25b7v 19b3v page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 vcc 1 osc gnd out single 50 pin for connection to ethernet card used on bottom of motherboard connectors ethernet (lan) i.m. card plug-connectors hierarchy block _phy_imbus_mb_dn phy_int osc25m mdc mdio pt2_tx_en pt2_rx_clk pt2_col_det pt1_tx_en pt1_tx_clk pt1_txd<3..0> pt1_rx_err pt1_rx_crs pt1_rxdv pt1_rx_clk pt1_col_det pt1_rxd<3..0> gmii_tx_er_ gmii_clktomac_buf spare gmii_clkfrom_mac reset_b pt2_tx_clk pt2_txd<3..0> pt2_rx_err pt2_rx_crs pt2_rxdv pt2_rxd<3..0> lan_clk v3_3 gmii only _phy_dp83865bvh_dn hierarchy block spare<4..1> clktomac_testpnt clktomac gmii_clkfrom_mac col_det rx_err phy_int rxd<7..0> txd<7..0> rxdv rx_clk rx_crs tx_clk tx_en tx_er_ reset_b mdio mdc phyosc25m lan_clk 26 5 4 3 1 conn_6p_u vcc 1 osc gnd out vcc 1 osc gnd out v3_3 v3_3 downloaded from: http:///
for ddr 11 ddr_ba0 ddr_ba1 ddr_cas ddr_ras ddr_we ddr_cke ddr_ck ddr_cs ddr_ckinv ddr_ldm ddr_udm ddr_ldqs ddr_udqs ddr_dq<15..0> ddr_dq<15..0> ddr_vref ddr_a<12..0> ddr_vref 4.7uf 4.7uf .1uf .1uf .1uf .1uf 4.7uf 4.7uf 12 10 9 8 7 6 5 4 3 2 1 0 0 1 2 3 54 6 7 8 9 10 11 12 14 13 15 1.00k 1.00k .01uf .01uf 4.7uf 4.7uf 0 1 2 3 4 5 6 7 8 9 10 11 12 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ddr_cs ddr_ck ddr_ldm ddr_cke ddr_ckinv ddr_cas ddr_ba0 ddr_ba1 ddr_ras ddr_we ddr_udm ddr_udqs ddr_ldqs .01uf .1uf 4.7uf cb75 cb76 cb72 c08 rb12 rb13 u06 29 28 41 42 30 31 32 35 36 37 38 39 40 26 27 22 45 46 44 24 50 19 2 57 59 60 62 63 65 4 5 7 8 10 11 13 54 56 20 16 17 43 14 25 53 23 47 51 1 18 33 55 3 15 9 61 49 66 48 34 52 64 58 12 6 21 cb58 cb102 cb49 cb90 cb83 cb85 cb146 cb89 cb74 cb110 cb63 u05 d12 c13 d13 c14 a14 b13 a13 a12 b11 c12 a11 b10 c11 d11 d9 b9 a9 a10 d10 c3 c4 d4 c5 d5 c6 d6 d7 a7 b6 a6 a5 b5 b4 a4 a3 b8 c7 c10 a8 b7 c9 b12 ddr_a<12..0> 10/03/2007 7/26(total) 7/12(block) cr-7 : @\_rc_lib\.\_rc_top_dn_\(sch_1):page7 DS33M33DK01a0 steve scully ddr memory. p.7 block name: _rc_top_dn_. 7b8 7b8 7b8 7b8 7b8 7b8 7b8 7b8 7b8 7b8 7a8 7c5 7c5 7a4 7a1 7c4 10b3 7d2 7c8 10b3 7d5 7c3 7c3 7c3 7c3 7c3 7c3 7b3 7c3 7c3 7c3 7c3 7c1 7c1 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 sdram i/f ds33m33_u sdudm sdwe* sdras* sdba[1] sdba[0] sda[1] sda[0] sda[4] sda[3] sda[2] sda[6] sda[5] sda[9] sda[7] sda[8] sda[11] sda[10] sda[12] sdcas* sdclkn sdclken sdldm sdclkp sdcs* sddq[0] sddq[2] sddq[1] sddq[3] sddq[5] sddq[4] sddq[6] sddq[7] sddq[8] sddq[9] sddq[10] sddq[11] sddq[12] sddq[13] sddq[14] sddq[15] sdudqs sdldqs v2_5 mt46v16m16bg75 a8 a9 a10/ap a11 a12 a1 a2 a3 a4 a5 a6 a7 ba0 ba1 cas ras we cke ck cs ck_inv ldm udm dnu dnu nc nc nc nc nc vssq vssq vssq vssq vssq vss vss vss vdd vdd vdd vddq vddq vddq vddq vddq vref a0 dq0 dq1 dq3 dq2 dq6 dq4 dq5 dq7 dq8 dq9 dq11 dq10 dq13 dq14 dq12 ldqs dq15 udqs v2_5 v2_5 downloaded from: http:///
remove this inverter to make use of the jumper options for ale (above) as testpoints for proto board (not needed) instantiate pullup for int in fpga mt0 & mt2 attaced to rpack double check bias needs for mt1 ale should be tied high for non-multiplexed address operation and tied tied low during spi mode (spisel=1). m3x_jtms cs_x1 m3x_cs jmp_3 13 m3x_cs d2_spi_clk data<7..0> spi_ss 2 jmp_3 inverter m3x_int m3x_int rd_ds 13 wr_rw 5 1k 10k 1 data<7..0> d7_spi_cpol data<7..0> data<7..0> d0_spi_miso spi_sck 7 6 5 1 0 jmp_3 10k 330 1k 10k 4 28 6 10 12 0 3 5 7 9 11 addr<13..0> 4 3 1 10 12 0 14 7 9 11 15 data<15..0> 28 6 d5_spi_swap 10k 1k d6_spi_cpha m3x_mt0 m3x_mt1 m3x_mt2 m3x_ale m3x_rmiisel m3x_dcesel m3x_hiz_n m3x_spisel m3x_test_en m3x_ifsel_style m3x_ifsel_size m3x_jtrst_n m3x_spisel m3x_ale m3x_jtdi m3x_jtdo spi_miso jmp_3 data<7..0> d1_spi_mosi spi_mosi data<7..0> 1k m3x_jtclk rpb50 4 3 2 1 5 6 7 8 j30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 rpb52 4 3 2 1 5 6 7 8 rpb53 4 3 2 1 5 6 7 8 ds28 j16 1 2 3 4 5 6 7 8 9 10 rpb32 4 3 2 1 5 6 7 8 jp11 1 3 2 jp14 1 3 2 jp13 1 3 2 jp12 1 3 2 rpb36 4 3 2 1 5 6 7 8 jp22 1 3 2 jp21 1 3 2 jp20 1 3 2 rpb33 4 3 2 1 5 6 7 8 ub05 1 4 rpb49 4 3 2 1 5 6 7 8 rpb48 4 3 2 1 5 6 7 8 rpb29 4 3 2 1 5 6 7 8 j24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 j21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 j23 1 2 3 4 5 6 7 8 9 10 bias+config. p.8 cr-8 : @\_rc_lib\.\_rc_top_dn_\(sch_1):page8 8/26(total) 8/12(block) DS33M33DK01a0 steve scully 10/03/2007 block name: _rc_top_dn_. 8c2 1a8 1d3 1a8 8d3 1b5 8d4 8c6 1d3 8c1 1d3 1b8 8a8 9c1 10b5 1a8 1d3 9c1 10b5 1a8 1d3 1b1 9c3 10b5 1a8 8b3 8c6 8d3 1b1 9c3 10b5 1a8 8b3 8d3 8d4 8d6 1b1 1b1 9c3 10b5 1a8 8b3 8c6 8d3 8d6 9c3 10b5 1a8 8b3 8c6 8d3 8d4 8d6 1b1 9c3 10b5 1a8 8b3 8c6 8d3 8d4 8d6 1b1 9c3 1a8 8b3 1c1 1a5 1a2 9c1 10b5 1a8 1b1 9c3 10b5 1a8 8c6 8d3 8d4 8d6 1c1 1c1 1b5 1b5 1b5 8a2 1a8 1d3 5a4 1b5 1c5 8a2 1b5 8b2 1a8 1d3 1c5 1d3 1a5 10b5 8d6 1b5 8d6 8d4 1c1 1c1 1c5 1c5 1c5 1b8 8d4 1b1 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 6 10 8 4 1 2 3 5 7 9 conn_10p conn_16p 24 8 10 12 14 16 3 1 7 9 11 13 15 5 6 v3_3 2 3 7 13 8 59 11 6 4 10 12 14 1 conn_14p v3_3 v3_3 nc7sz86_u v3_3 v3_3 2 3 7 13 8 59 11 6 4 10 12 14 1 conn_14p v3_3 conn_10p 5 3 1 7 tms tck tdi tdo vcc gnd downloaded from: http:///
databus taps wrong [0:7] this has been fixed in the fpga. bug fix: pcb rev 01a0 had the place testpoints to allow loopbak t--r port / pin assignments ds33m33_rclk1 is at pin f3 ds33m33_rclk3 is at pin j2 ds33m33_rclk2 is at pin h3 m33_tneg3 m33_tpos3 data[7..0] te3_int wr_rw rd_ds 330 m33_tpos1 m33_tclk2 m33_tpos2 addr[5..0] reset_sys 5 4 3 2 1 330 m33_tneg3 m33_rclk3 m33_rneg3 m33_tclk3 m33_rpos3 m33_tpos3 m33_gpiob3 m33_gpioa3 m33_rclk2 m33_rneg2 m33_tclk2 m33_rpos2 m33_gpiob2 m33_gpioa2 m33_rclk1 m33_rneg1 m33_tclk1 m33_rpos1 m33_tpos1 m33_gpiob1 m33_gpioa1 m33_tneg1 m33_tneg1 m33_tclk1 m33_rneg1 m33_rclk1 m33_rpos1 m33_rneg2 m33_rclk2 m33_rpos2 m33_rneg3 m33_rclk3 m33_rpos3 m33_tneg2 1k 1k 10k 10k m3x_clka red_green m33_gpiob1 m33_gpioa1 m33_gpioa3 m33_gpiob3 m33_gpioa2 m33_gpiob2 m33_tclk3 0 1 2 3 45 6 7 m33_tneg2 m33_tpos2 m3x_clkb te3_l_cs 0 m3x_cladclk_to_liu red_green red_green j12 1 2 3 4 5 6 j14 1 2 3 4 5 6 j17 1 2 3 4 5 6 j18 1 2 3 4 5 6 j15 1 2 3 4 5 6 j13 1 2 3 4 5 6 u05 g2 f2 f3 g4 e2 e3 f4 d2 u05 l4 k3 j2 k4 j3 j4 j5 k5 u05 h5 j6 h3 h4 h2 g3 h6 g5 rpb05 4 3 2 1 5 6 7 8 rpb02 4 3 2 1 5 6 7 8 ds07 1 2 3 4 ds06 1 2 3 4 ds01 1 2 3 4 rpb07 4 3 2 1 5 6 7 8 rpb04 4 3 2 1 5 6 7 8 j01 1 2 3 4 5 6 7 8 9 10 11 12 13 14 rpb13 4 3 2 1 5 6 7 8 rpb08 4 3 2 1 5 6 7 8 9/26(total) cr-26 : @\_rc_lib\.\_rc_top_dn_\(sch_1):page1_i9@\_rc _lib\.\_ds33m30dk_dn_\(sch_1):page7 04/15/2007 9/12(block) cr-9 : @\_rc_lib\.\_rc_top_dn_\(sch_1):page9 steve scully ds33m30m31m33ee01a0 t3e3 liu i/f. p.2,9,20-22 block name: _rc_top_dn_. 9a6 9a6 21d7v 21d3v 21c8v 21c7v 21c3v 21c2v 8d6 8d4 8d3 8c6 8b3 1a8 10b5 1b1 20d8v 1b8 21c8v 1d3 1a8 10b5 8c1 21c4v 1d3 1a8 10b5 8c1 9d6 9c6 9b6 21d6v 21d2v 21c6v 21c3v 21c2v 8b5 1a8 10b5 1a2 20b5v 1b5 1a8 11b3 10b4 9c4 9c1 9c1 9c4 9c1 9c4 10c4 9a5 10c4 9a5 9d1 9d1 9d4 9c1 10c4 9a5 10c4 9a5 9d1 9d1 9d4 9d1 9d4 10c4 9a5 10c4 9a5 9d4 9d6 9d6 9d8 9d8 9d8 9c8 9c8 9b8 9a8 9a8 9a8 9c6 20a3v 10b7 1d3 9a6 9d4 9c4 20a2v 10b7 1d2 21c4v 1a8 20a5v 6c6 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 2 3 7 13 8 59 11 6 4 10 12 14 1 conn_14p 2 1 3 4 2 1 3 4 2 1 3 4 v3_3 ds33m33_u port rlclk rneg/rlcv tlclk rpos/rdat tpos/tdat gpiob gpioa tneg ds33m33_u port rlclk rneg/rlcv tlclk rpos/rdat tpos/tdat gpiob gpioa tneg ds33m33_u port rlclk rneg/rlcv tlclk rpos/rdat tpos/tdat gpiob gpioa tneg 26 5 4 3 1 conn_6p_u 26 5 4 3 1 conn_6p_u 26 5 4 3 1 conn_6p_u 26 5 4 3 1 conn_6p_u 26 5 4 3 1 conn_6p_u 26 5 4 3 1 conn_6p_u _ds3154_liublock_dn hierarchy block addr0 data7 data6 data5 data4 data3 data2 data1 data0 liu_tpos1 liu_tneg1 e3_mclk_io t3_mclk_io alternate_mclk rst int rd_ds cs liu_tclk1 addr2 addr1 liu_rpos3 liu_rneg3 addr3 liu_tneg3 liu_tclk3 liu_tpos3 liu_rclk3 liu_tpos2 liu_tclk2 liu_tneg2 liu_rpos2 liu_rclk2 liu_rneg2 liu_rpos1 liu_rclk1 liu_rneg1 wr_rw addr4 addr5 downloaded from: http:///
m33_gpioa3 m3x_clkc m3x_clkb m3x_clka m3x_cladclk m33_gpiob2 m33_gpiob3 m33_gpiob1 m33_gpioa2 m33_gpioa1 reset_sys cpld_atohen cpld_taohen cpld_cs wr_rw cpld_atohclk cpld_atohsof cpld_dtoh cpld_dtohclk cpld_dtohsof cpld_taoh cpld_atoh cpld_oh1 cpld_ohclk cpld_rdoh cpld_rdohsof cpld_rdohvld cpld_taohsof cpld_taohvld rd_ds ddr_vref addr<3..0> data<7..0> u05 b16 a16 k1 m1 l1 n1 m15 f15 l15 e15 k15 d15 d1 f1 h1 p15 h15 e1 g1 j1 n15 g15 e5 e9 e12 e8 10/26(total) 10/03/2007 10/12(block) cr-10 : @\_rc_lib\.\_rc_top_dn_\(sch_1):page10 DS33M33DK01a0 steve scully overhead. p.2,10,23-24 block name: _rc_top_dn_. 23d6v 9a6 9a5 23d7v 6a7 1d2 23d7v 9b2 1d2 23d7v 9b2 1d3 23d7v 1d3 6c6 23d6v 9b6 9a5 23d6v 9a6 9a5 23d6v 9c6 9a5 23d6v 9b6 9a5 23d6v 9c6 9a5 23b4v 8d6 8d4 8d3 8c6 8b3 1a8 9c3 1b1 24b4v 1b5 1a8 11b3 9b1 23a5v 2b7 23a6v 2c7 23c7v 23b7v 8b5 1a8 9c1 1a2 23c7v 1a8 23c7v 1d3 1a8 9c1 8c1 23a5v 2b7 23a5v 2b7 23a5v 2b7 23a4v 2b7 23a5v 2b7 23a6v 2c7 23a5v 2b7 23a6v 2c7 23a6v 2c7 23a6v 2c7 23a5v 2c7 23a5v 2b7 23a6v 2c7 23a6v 2c7 23c7v 1d3 1a8 9c1 8c1 7d5 7d2 23c4v page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v1_8 v3_3 v1_8 v1_8 v2_5 overheadcpld_dn_ hierarchy block cpld_ohclk m33_gpiob2 m33_gpiob3 rd cp_dut_clkc cp_dut_clkb cp_dut_clka cp_dut_cladclk cpld_taohvld cpld_taohsof cpld_rdohvld cpld_rdohsof cpld_rdoh cpld_oh1 cpld_atoh cpld_taoh cpld_dtohsof cpld_dtohclk cpld_dtoh cpu_reset cpld_atohsof cpld_atohclk wr cpld_cs dat<7..0> addr<3..0> cpld_taohen cpld_atohen m33_gpioa1 m33_gpioa2 m33_gpioa3 m33_gpiob1 pwr & gnd ds33m33_u vdd33[6..1] vdd18[12..1] tvssa tvssb tvdd1_1_8v tvdd3_1_8v cvss1 vddp_2.5v vddp_2.5v vddp_2.5v avdd_1.8v vss[22..1] vssq[7..1] cvdd_1.8v cvdd_1.8v rhvssb cvss2 rhvssa tvss1 vref avss tvss3 tvss2 tvddb_1.8v rvddb_1.8v tvdda_1.8v hvddb_3.3v rvdda_1.8v hvdda_3.3v tvdd2_1_8v vddq_2.5v[7..1] downloaded from: http:///
trace geometry for this is: 1 inch long, 10 mil wide, 1 oz coppe r be long enough to build 0.05 ohm of resistance to ensure load sharing between the 2.5v 1% regulators traces between regulator output and v2.5 should 4.7uf 4.7uf .1uf .1uf .1uf .1uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf .1uf .1uf .1uf .1uf .1uf .1uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf .1uf .1uf .1uf 4.7uf 4.7uf 4.7uf green reset_sys 10uf 4.7uf .1uf .01uf .1uf .1uf 4.7uf 4.7uf 10uf 10uf .1uf .1uf 4.7uf 10uf 3.08v 330 .1uf .1uf .01uf 4.7uf 4.7uf 10uf 4.7uf .1uf .1uf .1uf 330 4.7uf 470uf .1uf 4.7uf 470uf .1uf 4.7uf 470uf 4.7uf 4.7uf 470uf 1.8v buffer 2.5v 4.7uf .1uf 4.7uf .1uf .1uf 4.7uf v1_8 4.7uf .1uf 4.7uf .1uf .1uf .1uf .1uf .1uf .1uf 4.7uf 10uf v2_5 green cb60 cb81 c12 cb61 cb108 cb86 cb35 cb104 cb50 cb80 cb82 cb91 cb51 cb111 cb99 cb87 cb109 cb52 sw01 1 2 3 4 ub07 1 3 2 4 rb28 ds30 1 2 cb57 cb56 cb59 cb170 c13 cb103 cb48 cb181 cb166 cb105 cb144 rb30 ds32 1 2 c16 cb145 1 2 ub12 1 4 c18 c23 cb171 1 2 ub08 10 17 2 3 45 12 13 14 15 6 11 7 cb156 cb175 cb174 1 2 cb163 cb150 cb157 1 2 ub09 10 17 2 3 45 12 13 14 15 6 11 7 cb55 cb71 cb06 cb05 cb12 cb128 cb138 cb25 cb119 cb133 cb141 cb14 cb131 cb123 cb120 cb122 cb115 cb116 cb142 cb118 cb126 cb127 cb136 cb26 cb27 cb04 cb117 cb03 cb140 cb187 cb186 cb132 cb182 c15 cb183 cb21 cb28 cb148 cb143 cb121 cb129 cb139 11/26(total) 10/03/2007 11/12(block) block name: _rc_top_dn_. parent block: cr-11 : @\_rc_lib\.\_rc_top_dn_\(sch_1):page11 DS33M33DK01a0 steve scully power. p.11-12 1b5 1a8 10b4 9b1 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 v3_3 v5_0 max1793_u in2 out1 out3 set gnd gnd in1 in3 in4 out2 shdn rst out4 max1793_u in2 out1 out3 set gnd gnd in1 in3 in4 out2 shdn rst out4 v1_8 nc7sz86_u v2_5 v3_3 v3_3 max811_u reset* vcc gnd mr* v3_3 v1_8 v2_5 v3_3 v3_3 v2_5 downloaded from: http:///
mouting hardware 3.3v 1% regulator 10uf 330 powerok .1uf 3.3v 3.3v 3.3v powerok 10uf 68uf 10uf 0.0 0.0 0.0 68uf 68uf 10uf 4.7uf .1uf .1uf 4.7uf .1uf 10uf 4.7uf .1uf .1uf 4.7uf .1uf .1uf 1 amp 68uf 10uf 10uf 10uf 10uf 100o100mzh 4.7uf 4.7uf 470uf red_green 10uf db01 2 1 c22 c20 cb188 cb155 cb161 cb167 cb152 cb151 cb162 cb169 cb149 cb180 cb190 cb179 cb172 cb173 cb13 c17 cb185 1 2 cb189 1 2 ub13 10 17 2 3 45 12 13 14 15 6 11 7 cb158 1 2 c24 r05 ds31 1 2 3 4 cb154 cb153 r04 r02 cb176 1 2 rpb59 4 3 2 1 5 6 7 8 c21 cb159 1 2 ub11 10 17 2 3 45 12 13 14 15 6 11 7 c19 gnd_tp01 ub10 10 17 2 3 45 12 13 14 15 6 11 7 gnd_tp02 gnd_tpb01 gnd_tp11 gnd_tpb02 gnd_tp04 gnd_tpb03 jb09 2 1 gnd_tp03 gnd_tpb06 hb03 hb01 hb02 hb05 hb04 l1 c1 block name: _rc_top_dn_. parent block: power. p.11-12 cr-12 : @\_rc_lib\.\_rc_top_dn_\(sch_1):page12 steve scully 10/03/2007 12/26(total) 12/12(block) DS33M33DK01a0 12a8 12a4 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v5_0 v5_0 max1793_u in2 out1 out3 set gnd gnd in1 in3 in4 out2 shdn rst out4 max1793_u in2 out1 out3 set gnd gnd in1 in3 in4 out2 shdn rst out4 v3_3 green red 3 2 1 4 v5_0 max1793_u in2 out1 out3 set gnd gnd in1 in3 in4 out2 shdn rst out4 v5_0 v3_3 downloaded from: http:///
beginning of processor hierarchy block 2 12 pd<31..0> osc_mcu once_tclk once_trst_b once_tms spi_mosi tim_16h_8l spi_cs cs1 eb0 14 15 22 2 pa<22..0> gnd 14 15 11 13 16 18 17 19 18 21 98 7 6 23 24 28 19 29 30 5 3 0 20 .1uf 0 1 4 21 3 5 6 7 98 10 11 12 13 22 20 25 sci2_in user_led2 run_kit_usr yco cs2 cse0 eb2 eb1 pqb1 eb3 cse1 2107_tdo once_tdi tc1 cs3 pqa1 pqa0 pqa3 pqa4 icoc22 icoc23 icoc20 icoc21 icoc11 icoc12 icoc13 test icoc10 sci2_out user_led1 tc2 1uf int2 pqb3 pqb2 pqb0 26 27 once_de_b spi_sck proc_reset_out cpuclk_out 4 10 31 0.0 cs0 reset_in 17 16 1 procser_in procser_out kit_status spi_miso xtal rw vddsyn flash_vpp tea vrh oe rcon ta 1b6^ 16c6 16c5 1b6^ 16b4 1a6^ 16c6 16b8 16c5 1a6^ 16c6 16c5 cb160 1 u09 50 49 11 6 139 137 136 134 132 131 122 121 47 119 117 116 29 28 26 24 23 14 13 51 48 36 35 34 31 30 27 25 22 21 20 46 17 16 15 12 10 7 5 4 3 2 43 1 144 42 41 40 39 38 37 95 59 97 99 102 9 19 33 45 65 77 129 141 115 74 103 123 87 113 112 8 18 32 44 64 76 127 140 114 73 126 92 u09 128 86 85 83 81 62 60 143 101 100 98 96 125 61 58 57 56 55 54 53 52 71 72 75 79 82 84 88 89 91 90 111 110 109 108 107 106 105 104 118 120 70 68 93 94 78 67 130 133 135 63 138 142 69 66 124 80 cb164 rb27 1/6(block) 10/03/2007 13/26(total) block name: _motprocrescard_dn. parent block: \_rc_top_d n_\ cr-13 : @\_rc_lib\.\_rc_top_dn_\(sch_1):page2_i10@\_r c_lib\.\_motprocrescard_dn\(sch_1):page1 DS33M33DK01a0 steve scully microport. p.1,13-18 14a2 15d3 15d6 15d5 16a1 14d7 14c7 14a5 16c4 14b7 16a3 16b4 14b4 15d5 15d5 1b8^ 14d2 17b7 15d4 16c4 14b7 14b4 1a8^ 18c2 15d5 14d1 17c7 15c8 15d6 16d2 15d3 16c4 14b7 14b4 14c7 15d4 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 out out in out mmc2107 control rxd1 int7* txd2 icoc10 test int1* icoc13 icoc12 icoc11 icoc21 icoc20 icoc23 icoc22 extal tclk trst* ss* pqb0 pqa4 pqa3 pqa0 pqa1 cs3* tc1 tdi tdo cse1 eb3* int6* pqb1 pqb2 pqb3 eb0* eb1* eb2* tc2 cse0 cs1* cs2* de* sck rstout* clkout reset* cs0* tms int0* yc0 mosi miso xtal int3* int2* int5* int4 rxd2 txd1 mmc2107 port ta* shs* oe* vrh vstby tea* vddh vddf vdda vpp vdd6 vdd7 vdd8 vddsyn vdd3 vdd5 rw vrl a8 d31 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a7 a6 a5 a4 a3 a2 a1 a0 vss1 vss2 vss3 vss4 vss5 vss6 vss7 vss8 vsssyn vssf vssa d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 vdd2 vdd1 vdd4 v3_3 downloaded from: http:///
(not used in this design) null nets d18 has a 10k load to gnd when set for master mode flash enable internal full drive boot internal xtal w/ pll reset configuration boot intern/extern 19 18 reset_out reset_in int4 int2 10k i219 d_dut<7..0> enable_drv cs_x1 wr_rw misc_io<8..1> misc_io<9> rd_ds cs_x2 cs_x3 15 pd<31..24> 24 25 22 cs0 oe eb1 pd<23..16> 20 17 16 3 1 2 4 5 6 i203 19 18 17 16 10 9 7 8 pa<19..1> 26 27 28 29 30 31 cs0 oe eb0 i142 18 19 16 17 15 65 4 2 1 3 7 13 14 11 12 10 9 pa<19..1> 8 cy62148v pd<19> pd<18> 10k pd<28> pd<23> pd<22> 10k pd<16> pd<26> pd<17> pd<21> 10k rcon a_dut_<13..0> 23 21 misc_io<10> misc_io<11> misc_io<12> enable_clbk cy62148v en_source_time proc_oscin int3 1a8^ 16a3 1a8^ 18c2 15d5 13b5 1b8^ 17b7 1b8^ 17b7 13a7 1a8^ 17a5 17d3 1a8^ 17c3 1a8^ 17c3 1a8^ 17c3 1a8^ 17c7 1a8^ 17c7 1a8^ 17a4 17d3 17c3 1a8^ 17c7 1b8^ 17c7 14 13 12 11 rpb61 4 3 2 1 5 6 7 8 rpb62 4 3 2 1 5 6 7 8 rpb57 4 3 2 1 5 6 7 8 u12 12 11 23 25 4 28 3 31 2 1 30 10 9 8 7 6 5 27 26 22 16 13 14 15 17 18 19 20 21 24 32 29 u11 12 11 23 25 4 28 3 31 2 1 30 10 9 8 7 6 5 27 26 22 16 13 14 15 17 18 19 20 21 24 32 29 rpb56 4 3 2 1 5 6 7 8 14/26(total) steve scully 10/03/2007 2/6(block) block name: _motprocrescard_dn. parent block: \_rc_top_d n_\ cr-14 : @\_rc_lib\.\_rc_top_dn_\(sch_1):page2_i10@\_r c_lib\.\_motprocrescard_dn\(sch_1):page2 DS33M33DK01a0 microport. p.1,13-18 16a1 14d7 14c7 13a2 16c4 14b7 13b5 16c4 14b7 13d3 16b4 13d7 16a1 14d7 14c7 13a2 16d4 14a8 13a1 16d4 14a5 13a1 16a1 14a2 13a2 16a1 14a5 13a2 16a1 14a2 13a2 16a1 14a2 13a2 16a1 14a2 13a2 16a1 14a5 13a2 16a1 14a2 13a2 16a1 14a2 13a2 13d3 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 v3_3 out out in in in in in cy62148v 4-mbit (512k x 8) io3 io2 io0 io1 io6 io5 io4 io7 gnd ce1* vcc a17 a18 we* oe* a16 a15 a8 a9 a10 a11 a12 a13 a14 a0 a1 a2 a3 a4 a5 a6 a7 cy62148v 4-mbit (512k x 8) io3 io2 io0 io1 io6 io5 io4 io7 gnd ce1* vcc a17 a18 we* oe* a16 a15 a8 a9 a10 a11 a12 a13 a14 a0 a1 a2 a3 a4 a5 a6 a7 io io io io io io out out out in out out out in v3_3 downloaded from: http:///
dtr and rts connection as but do not populate place pads for cap vdd is a (unused) output use rpack testpoints on cp2101 chip align key uart_digout prt1_in prt1_out prt1_in prt1_out uart_digin procser_out uart_digout usb_din usb_dout sspl usb_dout sspl usb_din 10k 1uf 10k 10k con14p once_trst_b 330 once_tms once_tdi 2107_tdo reset_in flash_vpp once_tclk 1.0m 8.0mhz osc_mcu xtal green kit_status 10k once_de_b usb procser_in .1uf 4.7uf 10k uart_digin j33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ub14 13 14 15 16 10 5 18 28 6 20 1 4 7 3 19 11 12 17 9 j34 1 2 3 45 6 7 89 r03 1 2 1 xb01 2 1 jb08 2 1 rpb64 4 3 2 1 5 6 7 8 rpb63 4 3 2 1 5 6 7 8 rb26 1 2 1 ds29 1 2 rpb58 4 3 2 1 5 6 7 8 rpb60 4 3 2 1 5 6 7 8 u10 23 1 27 28 3 10 21 22 13 14 15 16 17 18 19 20 7 2 9 24 25 12 11 26 54 8 6 cb184 1 2 cb177 1 2 cb178 1 2 rb29 1 2 j35 1 2 3 4 5 jp25 1 3 2 jp26 1 3 2 3/6(block) 15/26(total) DS33M33DK01a0 block name: _motprocrescard_dn. parent block: \_rc_top_dn_\ 10/03/2007 cr-15 : @\_rc_lib\.\_rc_top_dn_\(sch_1):page2_i10@\_r c_lib\.\_motprocrescard_dn\(sch_1):page3 steve scully microport. p.1,13-18 15a5 15a8 15a8 15b8 15b8 15a5 16b5 13b8 15b8 15b2 15b2 15b2 15a5 15b4 15b5 13a6 13a6 13d6 13d6 1a8^ 18c2 14d1 13b5 13a6 13a6 13a7 17c7 13a7 13b5 16b5 13b8 15b8 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 cp2101 usbdm suspend_low* suspend_high rxd txd vdd gnd nc1 nc2 nc3 nc5 nc4 nc6 regin rst* nc11 nc10 nc9 nc8 nc7 ri* dcd* dsr* cts* dtr* rts* usbdp vbus v3_3 v5_0 v3_3 v3_3 conn_db9p h g f c a b de j max3233e invalid* t2in t2out gnd v- c2- c2+ c1- c1+ v+2 v+1 forceoff* vcc t1out r1out forceon t1in r1in r2out r2in v3_3 gnd dat- vdd dat+ usb con14p downloaded from: http:///
this memory is for serial boot (if used) 19 18 17 2 1 04 12 5 19 31 30 29 28 26 14 11 9 10 8 7 6 3 24 21 20 18 17 16 10k spi_sck 25 23 pd<31..16> 13 pa<19..0> 27 i36 97_io rw procser_out procser_in eb1 spi_cs spi_miso spi_mosi oe cs0 eb0 proc_cs spi_sck cs2 reset_out i37 3.3v spi_mosi spi_miso spi_sck proc_cs i40 u08 25 45 46 52 53 55 56 57 58 59 60 62 63 65 66 67 68 69 70 71 72 37 38 40 41 43 44 49 50 12 13 14 15 17 18 19 20 23 24 26 27 28 1 2 3 45 7 8 10 ub06 1 4 7 6 52 8 3 rpb54 4 3 2 1 5 6 7 8 4/6(block) 10/03/2007 steve scully 16/26(total) DS33M33DK01a0 cr-16 : @\_rc_lib\.\_rc_top_dn_\(sch_1):page2_i10@\_r c_lib\.\_motprocrescard_dn\(sch_1):page4 microport. p.1,13-18 block name: _motprocrescard_dn. parent block: \_rc_top_d n_\ 1a6^ 16c6 16c5 13b5 14a2 14a5 14d7 13a1 14a5 14a8 14c7 13a2 1a8^ 14d1 13c5 1a6^ 16c6 16b8 13b5 16c6 14b7 13d7 13b5 14b7 14b4 14b7 14b4 13d3 1b6^ 13a7 16c6 13a7 16c6 1a6^ 1b6^ 13b5 14b4 13d7 15a7 13b8 15a7 13b8 13d4 1b6^ 16c5 13a7 13a7 16c5 1a6^ 16b8 1a6^ 16c5 13b5 16b5 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 at26df081_u 8mbit sck si gnd wp* hold* vcc so cs* lattice fpga lfe2-6-t144 pb2a (vref2_5) pb4a pb2b (vref1_5) pb4b pb6a (bdqs6*) pb6b nc nc pl8a pl8b pb14a pl2a (vref2_7) pl2b (vref1_7) pl4b pl4a pl6a pl6b pl12b pl12a pl13b (pclkc7_0) pl13a (pclkt7_0) pb22b pb20a pb22a pb20b pb13a(pclkt4_0) pb28b(vref1_4) pb13b(pclkc4_0) pb24a (bdqs24*) pb28a(vref2_4) pb18a pb16b pb16a pb14b pl22a pb8a(pclkt5_0) pb8b(pclkc5_0) pb18b pb26b pb24b pb26a pl15a (pclkt6_0) pl15b (pclkc6_0) pl16a (vref2_6) pl16b (vref1_6) pl18a (llm0_gdllt_fb_a) llm0_pllcap pl18b (llm0_gdllc_fb_a) pl20a (llm0_gpllt_in_a**) pl20b (llm0_gpllc_in_a**) downloaded from: http:///
cs_x1 rd_ds wr_rw ale_dut 1a8^ 2 cpuclk_out pd<31..16> 22 16 15 1 3 6 5 4 3 2 1 13 12 11 10 6 48 7 59 0 d_dut<7..0> 7 0 97_io cs_x3 enable_drv enable_clbk cs_x2 int4 proc_oscin kit_status int2 mem_so pa<19..0> a_dut_<13..0> int3 u08 124 103 101 100 99 98 97 96 92 91 84 82 80 108 107 134 131 130 129 126 125 123 122 121 119 118 116 115 114 113 112 111 110 109 144 143 141 140 137 136 93 block name: _motprocrescard_dn. parent block: \_rc_top_d n_\ 5/6(block) 10/03/2007 steve scully DS33M33DK01a0 31/39(total) cr-17 : @\_rc_lib\.\_rc_top_dn_\(sch_1):page2_i10@\_r c_lib\.\_motprocrescard_dn\(sch_1):page5 microport. p.1,13-18 127 104 1a8^ 14c1 1a8^ 14c1 1a8^ 14c1 14a8 14a5 13a1 1b8^ 13a7 14d2 1a8^ 14c1 13a7 15c8 14d1 1a8^ 1b8^ 14c1 1a8^ 14b1 14c1 14c1 1a8^ 14d2 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 out lattice fpga bank 2 bank 3/8 bank 1 bank 0 lfe2-6-t144 pr16b (vref2_3) pr16a (vref1_3) pr17b (rlm0_gdllc_in_a**) pr17a (rlm0_gdllt_in_a**) pr26a (d6) pr25b (d7) spi_mosi pr29a (d0) pr15a (pclkt3_0) pr15b (pclkc3_0) pr20a (rlm0_gpllt_in_a**) pt12b(pclkc1_0) pt14a pt14b pt16a pt18a pt18b pt20a pt20b pt22a pt22b pt24a pt24b pt26a pt26b pt28a(vref1_1) pt28b(vref2_1) pr13b (pclkc2_0) pr13a (pclkt2_0) pr2a (vref1_2) pr2b (vref2_2) pt10b(pclkc0_0) pt10a(pclkt0_0) pt6b pt6a pt4b pt4a pt2b (vref2_0) pt2a (vref1_0) pt12a(pclkt1_0) rlm0_pllcap pr20b (rlm0_gpllc_in_a**) nc nc downloaded from: http:///
v1_2 v1_2 .1uf .1uf 10uf mem_sck 10k l_tdo 10k 97_io 10uf .1uf mem_sck i23 i15 l_tms l_tck l_tdo l_tdi i13 i5 mem_cs mem_si mem_sck 2.7v l_tdi l_tms l_tck i9 l_tms l_tck 10uf mem_cs reset_in mem_si mem_so rb18 u08 78 77 73 74 79 11 21 30 47 51 61 81 95 105 120 133 138 76 88 87 86 75 32 33 34 36 16 29 48 54 83 102 128 135 94 22 6 39 90 142 139 117 106 89 64 42 31 9 85 35 132 cb130 rpb51 4 3 2 1 5 6 7 8 j31 1 2 3 4 5 6 7 8 9 10 ub04 1 4 7 6 52 8 3 cb125 cb124 cb137 cb135 cb134 ub03 2 5 1 64 3 cr-18 : @\_rc_lib\.\_rc_top_dn_\(sch_1):page2_i10@\_r c_lib\.\_motprocrescard_dn\(sch_1):page6 10/03/2007 block name: _motprocrescard_dn. parent block: \_rc_top_d n_\ 31/39(total) 3/5(block) steve scully DS33M33DK01a0 microport. p.1,13-18 18a5 18c3 18b2 18b7 18c4 18b5 18b2 18b2 18b2 18b5 18d6 18b5 18d6 18c6 18c6 18b7 18b5 18c4 18d6 18c4 18d6 18c4 18b5 18c4 18b5 18c4 18b2 18b7 18b7 13b5 14d1 15d5 1a8^ page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 v3_3 for spi all low connect xres to gnd with 1% 10k res 1.2v core vcc bank_8 pr25a spi_cs(di/csspon) vccio8 vccio7 vccio6 vccio5 vccio3 vccio4 vccio2 vccio1 vccio0 vccaux vccaux vccaux vccj vccaux vcc vcc gnd gnd gnd gnd gnd vcc vcc vcc vcc vcc vcc vcc gnd gnd gnd gnd gnd gnd gnd tdi tdo tck tms vcc cfg0 cfg1 cfg2 programn initn spiclk cclk done pr24a miso (busy/sispi) pr24b (dout/cson) xres v3_3 max1963 shdn* gnd rst* out ic in v3_3 at25160a_u si gnd wp* hold* vcc so sck cs* conn_10p 7 1 5 gnd 3 tck tms tdi vcc tdo downloaded from: http:///
connectors for lan motherboard to resource card begin/end phy connector hierarchy block phy_int pt2_tx_clk sfm-125-l2-s-d-lc gmii_clktomac_buf lan_clk mdc reset_b mdio pt2_tx_clk pt2_tx_en pt2_tx_en na i130 pt1_txd<3..0> pt1_rxdv pt1_rx_err pt1_col_det 3 lan_clk pt1_rx_crs pt1_rx_crs mdio v3_3 gnd gmii_tx_er_ pt1_rxd<3..0> pt2_txd<3..0> pt2_tx_clk pt2_rx_clk pt2_col_det pt2_rx_err pt2_rx_crs pt2_rxd<3..0> pt2_rxdv pt1_rxdv pt1_txd<3..0> pt1_tx_en pt1_tx_clk pt1_rx_clk pt1_col_det pt1_rx_err pt1_rx_crs i67 i68 gmii_clkfrom_mac spare gmii_clktomac_buf 0 1 2 3 0 1 2 3 0 1 2 0 1 2 3 na smt i78 pt1_rxd<3..0> pt1_txd<3..0> pt2_rxd<3..0> pt2_txd<3..0> pt1_tx_clk pt1_tx_en gmii_tx_er_ osc25m pt2_tx_en mdio mdc pt1_rx_clk phy_int spare pt2_rx_crs pt2_rx_clk pt2_col_det pt2_rx_err lan_clk pt1_col_det pt2_rxdv pt1_rx_err gmii_clkfrom_mac reset_b 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 smttp na_notpopulated pt1_rxd<3..0> pt2_txd<3..0> pt1_tx_clk pt1_tx_en gmii_tx_er_ gmii_clktomac_buf osc25m mdc pt1_rx_clk phy_int spare pt2_rx_crs pt2_rx_clk pt2_col_det pt2_rx_err pt2_rxdv pt1_rxdv gmii_clkfrom_mac reset_b 6b1^ 19b8 19b4 6b1^ 19b8 19b4 19b6 19b2 6b1^ 19b8 19b4 6b3^ 19b4 6b3^ 19b8 pt2_rxd<3..0> jb03 1 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 2 45 46 47 48 49 50 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 jb02 1 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 2 45 46 47 48 49 50 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 block name: _phy_imbus_mb_dn. parent block: \_rc_top_dn_ \ 1/1(block) 10/03/2007 DS33M33DK01a0 19/26(total) cr-45 : @\_rc_lib\.\_rc_top_dn_\(sch_1):page5_i3@\_rc _lib\.\_phy_imbus_mb_dn\(sch_1):page1 steve scully ethernet. p.5-6,19,25-26 19c1 19a4 6b1^ 19b4 19a4 6b3^ 19a8 19c1 19a8 19c1 19b8 6c3^ 19b6 19b1 6c3^ 19c8 19d1 6d3^ 19c2 19c1 6c3^ 19d1 19b6 6d3^ 19d1 19c6 6b3^ 19b8 19a8 6d3^ 19d1 19c6 6d3^ 19d1 19c2 6d3^ 19c2 19c1 6c3^ 19c4 19d1 6c3^ 19b2 19b1 6c3^ 19b4 19c1 6c3^ 19d1 19c4 6c3^ 19d1 19c4 6b1^ 19b4 19a4 19c1 19b4 6b3^ 19a8 19a4 6b3^ 19a8 19a4 6d3^ 19d1 19c2 6b3^ 19b2 19a8 19b2 19a7 19c1 19b2 19c1 19a2 19c1 19a2 19c1 19a2 6b3^ 19b4 19a8 6d3^ 19d1 19c2 19c1 19b2 6c3^ 19d1 19b2 6b1^ 19b4 19a4 6b3^ 19c4 19a8 6d3^ 19c6 19c1 6c3^ 19b8 19c1 6c3^ 19d1 19c8 6c3^ 19d1 19c8 6b1^ 19b8 19a4 6b1^ 19b8 19a4 6b3^ 19a8 6d3^ 19d1 19c6 6b3^ 19b6 19a8 19b6 19a7 19b6 19c1 19a6 19c1 19a6 19c1 19a6 19b6 6d3^ 19c6 19c1 6b1^ 19b8 19a4 6b3^ 19c7 19a8 19c1 19c1 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v2_5 io v3_3 v1_8 io 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 24 23 22 21 17 11 7 4 25 26 20 19 9 1 8 16 12 10 2 14 3 6 5 18 15 13 io io io io io io v3_3 io io io io io io io io io io io io io v2_5 io io v3_3 v1_8 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 24 23 22 21 17 11 7 4 25 26 20 19 9 1 8 16 12 10 2 14 3 6 5 18 15 13 io io io io io io downloaded from: http:///
ds3254 or alternate_mclk: reg cacr[amcsel1:0]=00 for 19.44mhz reg cacr[amcsel1:0]=10 for 77.76mhz begin liu hierarchy block rst liu_alt_mclk liu_e3mclk 44.736mhz_3.3v 34.368mhz_5.0v .1uf 4.7uf t3osc liu_t3mclk e3_mclk_io e3osc liu_alt_mclk liu_t3mclk liu_e3mclk lui_hw 10k 330 red e3osc 30 1uh jtrst 10k liu_test jtdo jtrst jtdo jtdi oscsel jtdi jtms jtms jtclk liu_t3mclk .1uf t3osc 4.7uf liu_e3mclk ale mot lui_hw rst int liu_test jtclk oscsel liu_alt_mclk alternate_mclk 9b3^ 9b3^ 9b3^ t3_mclk_io u07 e12 j8 e9 e4 h4 j4 d5 d4 b3 c11 k2 l10 d9 j9 h1 m8 a5 d8 h9 j5 d6 h7 h8 j7 e5 e6 f4 f5 f6 g7 g8 g9 d7 h5 h6 j6 e7 e8 f7 f8 f9 g5 g4 g6 ds19 1 2 yb03 4 5 1 8 yb04 4 5 1 8 l02 c10 c09 c07 c14 jp15 1 3 2 jp18 1 3 2 jp19 1 3 2 jp17 1 3 2 rp09 4 3 2 1 5 6 7 8 rpb40 4 3 2 1 5 6 7 8 j32 1 2 3 4 5 6 7 8 9 10 rpb55 4 3 2 1 5 6 7 8 rpb38 4 3 2 1 5 6 7 8 block name: _ds3154_liublock_dn. parent block: \_rc_top_ dn_\ DS33M33DK01a0 20/26(total) steve scully 10/03/2007 1/3(block) cr-46 : @\_rc_lib\.\_rc_top_dn_\(sch_1):page13_i204@\ _rc_lib\.\_ds3154_liublock_dn\(sch_1):page1 t3e3 liu i/f. p.2,9,20-22 46b6 47a6 10b2^ 47a6 47d8 10b2^ 9b2^ 21a6 20c7 20c8 20a4 20c8 20b6 20a7 20c8 20c6 20a7 20b6 20a4 20c6 20a3 20b6 20a1 20b6 20a1 20c3 20b3 20b2 20a2 20b3 20b3 21b7 21b5 21b4 21b2 20a4 20b2 20c4 20b2 20b2 20c8 20a3 20a3 20c8 20a1 21c4 21d3 20c8 20b6 20b4 21b7 21b5 21b4 21b2 20a6 20c8 20b6 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 control ds3154 vdd12 vdd2 vdd1 vss1 vss2 vss3 vss4 vss5 vss6 vss7 vss8 vss9 vss10 vss11 vss12 vdd11 vdd10 vdd9 vdd8 vdd7 vdd6 vdd5 vdd4 vdd3 jtms jtclk jtdi jtdo hiz nc1 nc2 nc3 nc4 t3mclk e3mclk rst* tcinv test* rcinv stmclk tbin hw rbin jtrst* v3_3 v3_3 v3_3 out v3_3 1 vcc 5 tdi conn_10p gnd tdo tms tck 3 rst io io in io v3_3 vcc 1 osc gnd out vcc 1 osc gnd out downloaded from: http:///
ds3254 or port locations rlos1 is at pin a1 rlos2 is at pin m12 it is a spare port in this design ds3254 or ds3253 is recommended for ds33m33 port 4 of ds3254 is not used with ds33m33 ds3254 or rlos3 is at pin a12 ds3254 or liu_rpos4 liu_rclk3 liu_tclk3 data6 data4 rclk2 rxp2 rclk1 rpos1 rneg4 liu_tclk4 addr5 addr5 rxn2 liu_tpos2 liu_tneg2 rts2 addr4 rclk2 txp2 txn2 tdm2 tts2 prbs2 liu_tclk2 rneg2 rpos2 rlos2 txp1 txn1 rst liu_rneg3 liu_rpos3 liu_rclk3 liu_rclk4 liu_tclk4 liu_rclk4 cs int rclk1 rneg1 data0 liu_tclk1 data3 30 oscsel rxn3 rclk3 rpos3 rneg3 jmp_3 jmp_3 rclk4 liu_tclk3 rlos3 rpos3 rneg3 ale data2 rxp1 rxn1 prbs3 addr2 data7 data6 data1 rts1 rlos1 rpos1 txp3 tdm1 liu_tpos1 liu_rclk1 liu_tpos4 liu_tneg4 tdm3 tts1 rclk3 tts3 jmp_3 rpos4 30 oscsel 30 liu_rneg1 liu_rpos1 rneg1 prbs1 rxp3 mot txp4 tts4 prbs4 rpos4 rlos4 liu_rclk1 liu_tpos3 liu_tneg3 txn3 rts3 liu_tneg1 oscsel rneg4 liu_rneg4 liu_rpos4 liu_rclk4 txn4 rclk4 data4 tdm4 addr3 rts4 addr1 rxp4 rxn4 data5 addr0 jmp_3 rd_ds cs wr_rw oscsel liu_tclk2 addr2 addr3 addr4 data0 data1 data2 data3 data7 data5 rd_ds liu_tclk1 int liu_rclk2 liu_tneg4 liu_tclk4 liu_tpos4 liu_rneg4 wr_rw addr1 addr0 30 liu_rneg2 rpos2 rneg2 liu_rclk2 liu_rpos2 9c3^ 21d3 9c3^ 21d7 9c3^ 21d7 9c3^ 21c8 9c3^ 21c8 9c3^ 21c7 9c3^ 21c2 9c3^ 21c3 u07 k6 h2 m2 m3 j2 h3 m1 j1 k3 l3 l2 l1 k1 l6 m5 k4 l7 k7 j3 k5 l4 m4 l5 m7 m6 u07 c7 e11 a11 a10 d11 e10 a12 d12 c10 b10 b11 b12 c12 b7 a8 c9 b6 c6 d10 c8 b9 a9 b8 a6 a7 u07 g10 l8 l12 k12 l9 k8 m12 m9 k10 k11 l11 m11 m10 g11 h12 j10 f11 f10 k9 h10 j11 j12 h11 f12 g12 u07 f3 b5 b1 c1 b4 c5 a1 a4 c3 c2 b2 a2 a3 f2 e1 d3 g2 g3 c4 e3 d2 d1 e2 g1 f1 jpb01 1 3 2 jp23 1 3 2 jp24 1 3 2 jp16 1 3 2 rpb35 4 3 2 1 5 6 7 8 rpb37 4 3 2 1 5 6 7 8 rpb31 4 3 2 1 5 6 7 8 rpb44 4 3 2 1 5 6 7 8 jb07 1 2 3 4 5 6 21/26(total) 2/3(block) 10/03/2007 block name: _ds3154_liublock_dn. parent block: \_rc_top_ dn_\ DS33M33DK01a0 cr-47 : @\_rc_lib\.\_rc_top_dn_\(sch_1):page13_i204@\ _rc_lib\.\_ds3154_liublock_dn\(sch_1):page2 steve scully t3e3 liu i/f. p.2,9,20-22 47b7 47b5 47b4 47b4 47b5 47b7 47c3 10c2^ 47c3 10c2^ 47d2 10c2^ 47c2 10c2^ 47d6 10c2^ 47c8 10c2^ 47c3 10c2^ 47c4 10c2^ 46b6 46c7 10b2^ 46d8 47d8 10b2^ 47c6 10c2^ 21b2 21b3 21c3 21c6 22a5 21c8 21d8 21b2 21a4 9c2^ 21a8 22a5 22d8 9c2^ 21a8 22b5 22b5 22a7 22c8 22c8 22b7 22d5 22d5 21b2 21c1 21a4 21b2 21a3 9b2^ 21a6 20d8 21b8 21b8 9c3^ 21a8 21b5 21b4 21b2 20a6 20a4 22c3 21c4 21d4 21d4 21c3 22b7 21b4 21b4 20d8 9c3^ 21a8 22c5 22c5 22b8 9c2^ 21a8 9c3^ 21a8 9c3^ 21a8 9c3^ 21a8 22d8 22b7 21b8 22d3 21b7 21a4 21a4 22a7 22c8 22c8 21d3 21b7 21b5 21b2 20a6 20a4 21d8 22c8 22c3 20d8 22b3 22c8 22b8 22b7 22d3 22c8 21b7 21b5 21b4 20a6 20a4 21d3 21a3 21a3 21b2 21a3 22b3 9c3^ 21a8 22a7 9c2^ 21a8 22c8 9c2^ 21a8 22a3 22a3 9c3^ 21a8 9c2^ 21a8 9c2^ 21a6 9c2^ 21a6 21b7 21b4 21b2 20a6 20a4 21c5 21c6 21b5 21d1 21c1 21b2 21d1 21b2 21d6 21d6 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 in out in ds3154 port tpos tneg rja rts* rmon rlb rclk sts llb e3m rxp rxn txp txn tdm* tdsa tdsb tja tts* prbs tlbo tclk rneg rpos rlos* in in in io io io io io io ds3154 port tpos tneg rja rts* rmon rlb rclk sts llb e3m rxp rxn txp txn tdm* tdsa tdsb tja tts* prbs tlbo tclk rneg rpos rlos* io in in in in in io 26 5 4 3 1 conn_6p_u in in ds3154 port tpos tneg rja rts* rmon rlb rclk sts llb e3m rxp rxn txp txn tdm* tdsa tdsb tja tts* prbs tlbo tclk rneg rpos rlos* in in in in in in in out out out out out out out out out ds3154 port tpos tneg rja rts* rmon rlb rclk sts llb e3m rxp rxn txp txn tdm* tdsa tdsb tja tts* prbs tlbo tclk rneg rpos rlos* downloaded from: http:///
unused prbs signals access points for end liu hierarchy block 332 rxp1 rxp4 rxp2 txp2 txp4 rxp3 txp3 rlos4 rlos3 prbs3 prbs1 prbs4 tts3 tts1 rts3 10k 10k 330 330 10k red red 332 332 332 332 332 rxn3 rxn1 txn4 rxn4 txn2 rxn2 332 txn3 332 txp1 txn1 tts4 rts2 rts4 tts2 10k rts1 prbs2 rlos2 rlos1 330 tdm4 tdm2 tdm1 tdm3 rb21 rb19 j27 2 1 rb23 rb17 rb24 rb20 rb25 rb22 rpb47 4 3 2 1 5 6 7 8 rpb43 4 3 2 1 5 6 7 8 rpb39 4 3 2 1 5 6 7 8 ds20 1 2 ds22 1 2 ds25 1 2 ds27 1 2 rpb42 4 3 2 1 5 6 7 8 rpb41 4 3 2 1 5 6 7 8 ds21 1 2 ds23 1 2 ds24 1 2 ds26 1 2 rpb46 4 3 2 1 5 6 7 8 rpb45 4 3 2 1 5 6 7 8 t01 5 10 23 9 24 t01 6 12 21 11 22 t01 8 16 17 15 18 t01 7 14 19 13 20 t01 1 2 31 1 32 t01 2 4 29 3 30 t01 4 8 25 7 26 t01 3 6 27 5 28 j25 2 1 j22 2 1 jb06 2 1 j26 2 1 j29 2 1 j28 2 1 jb05 2 1 8/34(total) 04/15/2007 8/11(block) steve scully block name: _rc_top_dn_. parent block: \_rc_top_dn_\ ds33m30m31m33ee01a0 t3e3 liu i/f. p.2,9,20-22 cr-48 : @\_rc_lib\.\_rc_top_dn_\(sch_1):page13_i204@\ _rc_lib\.\_ds3154_liublock_dn\(sch_1):page3 21c8 21c3 21c6 21c5 21c2 21c4 21c3 21d3 21d4 21d3 21d7 21d2 21c3 21c7 21c5 21c4 21c8 21c2 21c3 21c5 21c6 21c3 21c7 21c7 21c2 21c6 21c3 21c5 21c8 21d5 21d6 21d8 21c2 21c5 21c7 21c3 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 g s g s g s g s g s g s g s g s 1:2 1:2 1:2 1:2 1:2 1:2 1:2 1:2 v3_3 v3_3 v3_3 downloaded from: http:///
mem_sck must be at pin77 for tqfp144 signals forsignals for hierarchy interface begin cpld hierarchy block mem_si cp_dut_clkc 7 65 4 3 20 dat<7..0> v3_3 gnd red_green 330 cp_dut_clka cp_dut_clkb 0 1 2 3 wr rd cpld_cs cpld_dtohsof cpld_atohclk cpld_atohen cpld_rdohvld cpld_ohclk cpld_oh1 cpld_taoh cpld_taohsof cpld_taohen cpld_taohvld cpld_rdoh cpld_atoh cpld_atohsof cpld_dtoh cp_dut_cladclk cpld_rdohsof cp_dut_clkb cp_dut_clkc m33_gpioa1 m33_gpiob1 m33_gpioa2 m33_gpiob2 m33_gpiob3 m33_gpioa3 m33_gpiob1 m33_gpioa2 m33_gpiob2 m33_gpioa3 m33_gpiob3 m33_gpioa1 mem_sck red_green red_green cp_dut_cladclk 1 97_io cpld_dtohclk mem_so mem_cs 0.0 addr<3..0> cp_dut_clka red_green 10b5^ rb04 u01 39 40 41 42 43 45 46 47 48 49 50 51 53 56 57 58 59 60 61 62 64 65 66 67 68 69 70 20 21 22 23 25 26 27 29 30 31 32 33 34 35 2 3 45 6 7 89 88 87 86 85 83 82 81 79 78 77 76 75 74 107 106 105 104 103 102 101 100 142 141 140 139 138 137 135 134 133 132 131 130 129 127 124 123 122 121 120 119 118 116 115 114 113 112 111 ds10 1 2 3 4 rp01 4 3 2 1 5 6 7 8 ds12 1 2 3 4 ds11 1 2 3 4 ds13 1 2 3 4 j02 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 23/26(total) steve scully 10/03/2007 1/2(block) DS33M33DK01a0 block name: overheadcpld_dn_. parent block: \_rc_top_dn_ \ overhead. p.2,10,23-24 cr-49 : @\_rc_lib\.\_rc_top_dn_\(sch_1):page12_i24@\_ rc_lib\.\overheadcpld_dn_\(sch_1):page1 11b5^ 11b5^ 11b5^ 11b5^ 11c5^ 11c7^ 11c5^ 11c5^ 11c5^ 11c7^ 11c7^ 11c5^ 11c5^ 11b7^ 11c7^ 11c7^ 11b7^ 11b7^ 11c7^ 11c7^ 49d7 11b7^ 49d7 11b7^ 49d7 11b7^ 49d7 11b7^ 24c8 10b7^ 23a3 10b7^ 23a3 10b7^ 23a3 24c8 24b8 10b7^ 23a3 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 bank 3 lfec_t144_u bank 0 i/o port bank 6 bank 4 bank 5 bank 1 bank 2 input pll pll input pll input bank 7 input pll input pll pll input pl9b/pclkc7_0 pt16b/vref1_0 pt17a/pclkt0_0 pt15a pt15b pt16a/vref2_0 pr14a/rlm0_pllt_fb_a pr12a/dout/cso* pt14b pl14a pl13b pl13a pt12b pt12a pb17a/pclkt5_0 pb19a/vref1_4 pb19b/cs* pb20a/vref2_4 pt14a/tdqs14 pt10a pt10b pb10b pb23a pb22a/bdqs22 pb21a/d2/spid5 pb18b/cs1* pl11a/llm0_pllt_in_a pl11b/llm0_pllc_in_a pl12a/llm0_pllt_fb_a pl12b/llm0_pllc_fb_a pl14b pl15b pl15a/ldqs15 pl16b pl18b/vref2_6 pl18a/vref1_6 pb18a/write* pb17b/pclkc5_0 pb16a/vref2_5 pb16b/vref1_5 pb15b pb15a pb14b pb14a/bdqs14 pb13b pb11b pb11a pb10a pl16a pb20b/d0/spid7 pb21b/d1/spid6 pb22b/d3/spid4 pb23b/d4/spid3 pb25b/d6/spid1 pb24b/d5/spid2 pl2a/vref2_7 pl2b/vref1_7 pl7a pl7b pl8b pl8a pt25b pt25a pt23a pt22b pt22a/tdqs22 pt21b pt20a pt21a pt20b pt19b/vref2_1 pt13b pt13a pt19a/vref1_1 pt18b pt18a pr2b/vref1_2 pr2a/vref2_2 pr7b pr7a pr8a pr8b pr9a/pclkt2_0 pr9b/pclkc2_0 pr13a/rlm0_pllt_in_a pr13b/rlm0_pllc_in_a pr14b/rlm0_pllc_fb_a pr15a/rdqs15 pr16a pr18a/vref1_3 pr16b pl9a/pclkt7_0 pr15b pt17b/pclkc0_0 pr11a/d7/spid0 pr11b/busy/sispi pr12b/di/csspi* io io io io io io in in in in conn_16p 24 8 10 12 14 16 3 1 7 9 11 13 15 5 6 g r 3 4 2 1 g r 3 4 2 1 g r 3 4 2 1 g r 3 4 2 1 in in in in in in in in in in in out out out in out in in in in io v3_3 downloaded from: http:///
end cpld hierarchy block mem_sck 10k 97_io 10k 10k 2.7v .1uf mem_cs mem_so mem_si i27 i18 l_tdi l_tdo l_tck l_tms cpu_reset l_tms l_tdo l_tdi l_tck i12 i3 i7 10k mem_sck 10uf 10uf 10uf .1uf .1uf i29 v1_2 v1_2 tpb02 1 rb03 rb05 tpb01 1 u01 94 91 90 89 97 128 117 98 109 72 80 63 52 28 37 144 15 96 95 11 12 93 14 16 18 17 13 92 99 54 126 136 143 110 125 108 73 84 55 71 38 44 24 36 1 19 10 cb02 rb02 rb01 jb01 1 2 3 4 5 6 7 8 9 10 cb01 cb08 cb09 cb10 cb11 ub02 1 4 7 6 52 8 3 ub01 2 5 1 64 3 DS33M33DK01a0 24/26(total) steve scully 2/2(block) 10/03/2007 block name: overheadcpld_dn_. parent block: \_rc_top_dn_ \ overhead. p.2,10,23-24 cr-50 : @\_rc_lib\.\_rc_top_dn_\(sch_1):page12_i24@\_ rc_lib\.\overheadcpld_dn_\(sch_1):page2 11b5^ 23b3 24b1 23b4 23c4 23c4 24c4 24c4 24c4 24c4 24d6 24d6 24d6 24d6 24a5 24c1 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 max1963 shdn* gnd rst* out ic in v3_3 at25160a_u si gnd wp* hold* vcc so sck cs* v3_3 conn_10p 7 1 5 gnd 3 tck tms tdi vcc tdo v3_3 v3_3 control lfec_t144_u all low for spi3 mode needs 10k,1% resistor place close to pin vccio4a vccio3b xres vccaux2 vccaux1 vccj vcc3 tdi tdo vccio3a vccio4b vccio5a vccio2 vccio1b vccio1a vccio0b init* program* vccio0a cclk cfg1 cfg2 cfg0 tms vcc2 vcc1 vccio5b vccio6a tck done gnd10 gnd9 gnd8 gnd7/gnd0 gnd6b/gnd5 gnd3b gnd3a/gnd4 gnd2/gnd1 gnd1 gnd0 nc1 nc2 gnd4 gnd6a gnd5 vccio7 vccio6b in downloaded from: http:///
begin phy hierarchy block close to phy stipline to v2_5phy maintain 50ohm place mdi resistors place 9.76k res close to bg_ref rxd[0:7] [pin56:pin45] txd[0:7] [pin76:pin65] rxdv pin44 output rxclk pin57 col pin39 crs pin40 rxer pin41 txclk pin60 clkin pin86 gtxclk pin79 clktomac pin85 clkout pin87 input mdc pin81 txerr pin61 txen pin62 2.0k 330 1k gnd a0_duplex 0603_2pct_50 30 30 30 0603_2pct_50 9.76k 30 1k green 30 30 2.0k v3_3 rxd<7..0> 7 6 5 4 3 2 1 0 rx_crs_buf tx_clk_buf tx_en gmii_clkfrom_mac tx_er_ rx_err_buf rxdv_buf txd<7..0> col_det_buf rx_clk_buf tx_er_ 7 6 5 4 3 2 1 0 bg_ref reset_b phyosc25m clkout_buf activityled_speed0 non_ieee_strap mdio mdc mdix_en_strap phy_int mdia_n mdib_p mdib_n mdia_p mdic_n mdid_p mdid_n mdic_p clktomac_buf tx_clk_buf clkout_buf rx_clk_buf col_det_buf rx_crs_buf rx_err_buf rxdv_buf clktomac rx_crs col_det clktomac_testpnt rx_clk tx_clk clkout rx_err rxdv rx_crs rxdv tx_en rx_clk tx_clk rx_err clktomac txd<7..0> rxd<7..0> col_det gmii_clkfrom_mac tx_er_ clktomac_testpnt phyosc25m lan_clk spare<4..1> phy_int mdio reset_b mdc link100led_duplex clktomac_buf man_mdix_strap__tx_tclk link10led_speed1 link1000led_anen 6d4^ 25a1 6d4^ 25a1 6c4^ 25b7 6d4^ 25b1 6c4^ 25b1 6c4^ 25a1 6c4^ 25b1 6c4^ 25b7 6d4^ 25a8 6d4^ 25b1 6c4^ 25b7 6c4^ 25b7 25a7 25b1 6b4^ 25b3 6b4^ 6b4^ 26c6 25c3 6b4^ 26c6 25c3 6b4^ 26c6 25d6 6b4^ 25c3 a0_duplex multi_en_strap__tx_trigger mac_clk_en_strap__tx_syn_clk u04 98 100 7 102 86 87 85 39 40 79 3 10 9 8 88 6 81 109 108 115 114 121 120 127 126 80 89 94 1 13 14 17 18 95 33 57 44 41 56 55 52 51 50 47 46 45 24 31 28 27 32 60 62 61 76 75 72 71 68 67 66 65 34 rp05 4 3 2 1 5 6 7 8 rp07 4 3 2 1 5 6 7 8 rp06 4 3 2 1 5 6 7 8 rpb25 4 3 2 1 5 6 7 8 rp12 4 3 2 1 5 6 7 8 rb16 ds18 1 2 rpb20 4 3 2 1 5 6 7 8 rb06 rb07 rp02 4 3 2 1 5 6 7 8 rb11 tpb03 rpb30 4 3 2 1 5 6 7 8 rpb26 1 2 3 4 8 7 65 rpb24 1 2 3 4 8 7 65 10/03/2007 1/2(block) 25/26(total) block name: _phy_dp83865bvh_dn. parent block: \_rc_top_d n_\ steve scully cr-25 : @\_rc_lib\.\_rc_top_dn_\(sch_1):page5_i23@\_r c_lib\.\_phy_dp83865bvh_dn\(sch_1):page1 DS33M33DK01a0 ethernet. p.5-6,19,25-26 92 90 96 123 128 25a3 6d4^ 25b1 25a2 25b2 6c4^ 25c1 6c4^ 25d1 6c4^ 25a7 25c1 25a2 25a2 6c4^ 25c1 25b2 25b2 6c4^ 25b7 25c1 25a4 6b4^ 26c6 25d2 6b4^ 25d1 25b2 26b6 26c4 26d4 6b4^ 26c6 25d2 6b4^ 25d2 26c4 26c3 26c3 26c3 26c3 26b3 26b3 26b3 26c3 25b3 25c7 25b3 25c7 25c7 25a7 25a7 6c4^ 25c1 6d4^ 25c1 6d4^ 25c1 6d4^ 25c1 6c4^ 25c1 6c4^ 25c1 6d4^ 25c1 26b6 25b2 26c4 26b6 26b6 26c4 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 io io io v3_3 io io io io io io io io io io io io in v2_5 v1_8 v2_5 v1_8 v3_3 io io io io dp83865_u vss<1..35> multi_en_strap/tx_trigger man_mdix_strap/tx_tclk link10_led/speed1_strap link100_led/duplex_strap link1000_led/an_en_strap mdix_en_strap phyaddr<1>_strap duplex_led/phyaddr<0>_strap activity_led/speed0_strap non_ieee_strap phyaddr<4>_strap mac_clk_en_strap/tx_syn_clk phyaddr<2>_strap phyaddr<3>_strap clk_to_mac mdib_n mdia_p interrupt* mdia_n mdc mdio clk_in mdid_n mdid_p mdic_n mdic_p mdib_p clk_out rx_dv/rck rx_er/rxdv_er rxd<7> rxd<6> rxd<5> rxd<4> rxd<3>/rx3 rxd<0>/rx0 rxd<2>/rx2 rxd<1>/rx1 rx_clk tx_er gtx_clk/tck tx_en/txen_er txd<7> txd<6> txd<5> txd<4> txd<2>/tx2 txd<3>/tx3 txd<0>/tx0 txd<1>/tx1 tx_clk/rgmii_sel0 crs/rgmii_sel1 col tms tck tdo tdi trst* reset* bg_ref vdd_sel_strap 1v8_avdd3 1v8_avdd2 1v8_avdd1_<1..5> 2v5_avdd<1..2> io_vdd<1..12> core_vdd<1..8> downloaded from: http:///
end phy hierarchy block caps for decouple of mx.+- strap options here do not follow datasheet check that 2.2k res use the same rpack .1uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf .1uf .1uf .1uf .1uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf .1uf .1uf .1uf .1uf .1uf .1uf .1uf .1uf .1uf .1uf .01uf .01uf .01uf 4.7uf 4.7uf 4.7uf .1uf .1uf .01uf mdia_p mdid_p mdic_n mdic_p mdid_n mdib_n l1000ob l100ob activityled_speed0 link10led_speed1 link100led_duplex link1000led_anen l10ob jmp_3 2.2k 2.2k green_green 330 jmp_3 jmp_3 2.2k green_green .01uf .01uf .01uf .01uf 4.7uf 4.7uf lactob 2.2k green_green green_green jmp_3 jmp_3 2.2k jmp_3 jmp_3 jmp_3 jmp_3 2.0k man_mdix_strap__tx_tclk multi_en_strap__tx_trigger mdix_en_strap mac_clk_en_strap__tx_syn_clk non_ieee_strap 2.2k phy_int mdio reset_b cb79 cb112 cb92 cb101 jp05 1 3 2 jp02 1 3 2 jp04 1 3 2 jp03 1 3 2 jp10 1 3 2 jp09 1 3 2 jp08 1 3 2 jp06 1 3 2 jp07 1 3 2 cb93 cb62 rpb21 4 3 2 1 5 6 7 8 rpb28 4 3 2 1 5 6 7 8 r01 rpb22 4 3 2 1 5 6 7 8 rpb19 1 8 rpb19 2 7 rpb19 3 6 rpb19 4 5 j11 1 10 2 3 45 6 7 89 11 12 ds15 1 2 3 4 ds16 1 2 3 4 ds17 1 2 3 4 ds14 1 2 3 4 cb67 cb66 cb68 cb168 cb53 cb64 cb113 cb54 cb45 cb95 cb47 cb44 cb88 c05 cb69 cb98 cb43 cb77 cb94 cb97 cb106 cb114 cb147 cb73 cb19 cb07 cb15 cb65 cb107 cb165 cb20 cb18 cb84 c11 c06 cb100 cb96 cb78 cb46 cb70 mdib_p mdia_n 26/26(total) 10/03/2007 2/2(block) DS33M33DK01a0 steve scully block name: _phy_dp83865bvh_dn. parent block: \_rc_top_d n_\ ethernet. p.5-6,19,25-26 cr-26 : @\_rc_lib\.\_rc_top_dn_\(sch_1):page5_i23@\_r c_lib\.\_phy_dp83865bvh_dn\(sch_1):page2 25c3 25c3 25c3 25b3 25b3 25c3 25b3 25c3 25b3 25b3 25b3 25b3 25b3 25a3 25a3 25a3 25b3 6b4^ 25d2 25c3 6b4^ 25d2 25c3 6b4^ 25d6 25d2 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 1000pf, 2kv mx3- mx3+ j8 j7 mx2- j5 j4 j6 j1 j2 mx0- mx0+ mx2+ j3 mx1- mx1+ 750 x4 cmr chokes 0.01 uf x4 conn_hfj11_1g02e_u vcc td0+ td1+ td0- td1- td2+ sh1 sh2 td3+ td3- gnd td2- v2_5 v2_5 v3_3 v3_3 v3_3 v3_3 v3_3 v3_3 v2_5 v1_8 v3_3 3 4 2 1 3 4 2 1 3 4 2 1 3 4 2 1 downloaded from: http:///

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